1 //===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // This describes the calling conventions for ARM architecture. 10 //===----------------------------------------------------------------------===// 11 12 /// CCIfAlign - Match of the original alignment of the arg 13 class CCIfAlign<string Align, CCAction A>: 14 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>; 15 16 //===----------------------------------------------------------------------===// 17 // ARM APCS Calling Convention 18 //===----------------------------------------------------------------------===// 19 def CC_ARM_APCS : CallingConv<[ 20 21 // Handles byval parameters. 22 CCIfByVal<CCPassByVal<4, 4>>, 23 24 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 25 26 // Handle all vector types as either f64 or v2f64. 27 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 29 30 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack 31 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>, 32 33 CCIfType<[f32], CCBitConvertToType<i32>>, 34 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 35 36 CCIfType<[i32], CCAssignToStack<4, 4>>, 37 CCIfType<[f64], CCAssignToStack<8, 4>>, 38 CCIfType<[v2f64], CCAssignToStack<16, 4>> 39 ]>; 40 41 def RetCC_ARM_APCS : CallingConv<[ 42 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 43 CCIfType<[f32], CCBitConvertToType<i32>>, 44 45 // Handle all vector types as either f64 or v2f64. 46 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 48 49 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>, 50 51 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 52 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 53 ]>; 54 55 //===----------------------------------------------------------------------===// 56 // ARM APCS Calling Convention for FastCC (when VFP2 or later is available) 57 //===----------------------------------------------------------------------===// 58 def FastCC_ARM_APCS : CallingConv<[ 59 // Handle all vector types as either f64 or v2f64. 60 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 62 63 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 64 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 65 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 66 S9, S10, S11, S12, S13, S14, S15]>>, 67 68 // CPRCs may be allocated to co-processor registers or the stack - they 69 // may never be allocated to core registers. 70 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 71 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>, 72 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>, 73 74 CCDelegateTo<CC_ARM_APCS> 75 ]>; 76 77 def RetFastCC_ARM_APCS : CallingConv<[ 78 // Handle all vector types as either f64 or v2f64. 79 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 80 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 81 82 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 83 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 84 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 85 S9, S10, S11, S12, S13, S14, S15]>>, 86 CCDelegateTo<RetCC_ARM_APCS> 87 ]>; 88 89 //===----------------------------------------------------------------------===// 90 // ARM APCS Calling Convention for GHC 91 //===----------------------------------------------------------------------===// 92 93 def CC_ARM_APCS_GHC : CallingConv<[ 94 // Handle all vector types as either f64 or v2f64. 95 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 96 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 97 98 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, 99 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, 100 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, 101 102 // Promote i8/i16 arguments to i32. 103 CCIfType<[i8, i16], CCPromoteToType<i32>>, 104 105 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim 106 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>> 107 ]>; 108 109 //===----------------------------------------------------------------------===// 110 // ARM AAPCS (EABI) Calling Convention, common parts 111 //===----------------------------------------------------------------------===// 112 113 def CC_ARM_AAPCS_Common : CallingConv<[ 114 115 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 116 117 // i64/f64 is passed in even pairs of GPRs 118 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register 119 // (and the same is true for f64 if VFP is not enabled) 120 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>, 121 CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8", 122 CCAssignToReg<[R0, R1, R2, R3]>>>, 123 124 CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>, 125 CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>, 126 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 127 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>, 128 CCIfType<[v2f64], CCIfAlign<"16", 129 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>, 130 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>> 131 ]>; 132 133 def RetCC_ARM_AAPCS_Common : CallingConv<[ 134 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 135 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 136 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 137 ]>; 138 139 //===----------------------------------------------------------------------===// 140 // ARM AAPCS (EABI) Calling Convention 141 //===----------------------------------------------------------------------===// 142 143 def CC_ARM_AAPCS : CallingConv<[ 144 // Handles byval parameters. 145 CCIfByVal<CCPassByVal<4, 4>>, 146 147 // The 'nest' parameter, if any, is passed in R12. 148 CCIfNest<CCAssignToReg<[R12]>>, 149 150 // Handle all vector types as either f64 or v2f64. 151 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 152 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 153 154 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>, 155 CCIfType<[f32], CCBitConvertToType<i32>>, 156 CCDelegateTo<CC_ARM_AAPCS_Common> 157 ]>; 158 159 def RetCC_ARM_AAPCS : CallingConv<[ 160 // Handle all vector types as either f64 or v2f64. 161 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 162 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 163 164 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>, 165 CCIfType<[f32], CCBitConvertToType<i32>>, 166 CCDelegateTo<RetCC_ARM_AAPCS_Common> 167 ]>; 168 169 //===----------------------------------------------------------------------===// 170 // ARM AAPCS-VFP (EABI) Calling Convention 171 // Also used for FastCC (when VFP2 or later is available) 172 //===----------------------------------------------------------------------===// 173 174 def CC_ARM_AAPCS_VFP : CallingConv<[ 175 // Handles byval parameters. 176 CCIfByVal<CCPassByVal<4, 4>>, 177 178 // Handle all vector types as either f64 or v2f64. 179 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 180 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 181 182 // HFAs are passed in a contiguous block of registers, or on the stack 183 CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>, 184 185 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 186 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 187 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 188 S9, S10, S11, S12, S13, S14, S15]>>, 189 CCDelegateTo<CC_ARM_AAPCS_Common> 190 ]>; 191 192 def RetCC_ARM_AAPCS_VFP : CallingConv<[ 193 // Handle all vector types as either f64 or v2f64. 194 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 195 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 196 197 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 198 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 199 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 200 S9, S10, S11, S12, S13, S14, S15]>>, 201 CCDelegateTo<RetCC_ARM_AAPCS_Common> 202 ]>; 203 204 //===----------------------------------------------------------------------===// 205 // Callee-saved register lists. 206 //===----------------------------------------------------------------------===// 207 208 def CSR_NoRegs : CalleeSavedRegs<(add)>; 209 210 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4, 211 (sequence "D%u", 15, 8))>; 212 213 // Constructors and destructors return 'this' in the ARM C++ ABI; since 'this' 214 // and the pointer return value are both passed in R0 in these cases, this can 215 // be partially modelled by treating R0 as a callee-saved register 216 // Only the resulting RegMask is used; the SaveList is ignored 217 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, 218 R5, R4, (sequence "D%u", 15, 8), 219 R0)>; 220 221 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register. 222 // Also save R7-R4 first to match the stack frame fixed spill areas. 223 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>; 224 225 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4, 226 (sub CSR_AAPCS_ThisReturn, R9))>; 227 228 // The "interrupt" attribute is used to generate code that is acceptable in 229 // exception-handlers of various kinds. It makes us use a different return 230 // instruction (handled elsewhere) and affects which registers we must return to 231 // our "caller" in the same state as we receive them. 232 233 // For most interrupts, all registers except SP and LR are shared with 234 // user-space. We mark LR to be saved anyway, since this is what the ARM backend 235 // generally does rather than tracking its liveness as a normal register. 236 def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>; 237 238 // The fast interrupt handlers have more private state and get their own copies 239 // of R8-R12, in addition to SP and LR. As before, mark LR for saving too. 240 241 // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and 242 // current frame lowering expects to encounter it while processing callee-saved 243 // registers. 244 def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>; 245 246 247
