1 //=- MicroMips64r6InstrFormats.td - Instruction Formats -*- tablegen -* -=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes microMIPS64r6 instruction formats. 11 // 12 //===----------------------------------------------------------------------===// 13 14 class DAUI_FM_MMR6 { 15 bits<5> rt; 16 bits<5> rs; 17 bits<16> imm; 18 19 bits<32> Inst; 20 21 let Inst{31-26} = 0b111100; 22 let Inst{25-21} = rt; 23 let Inst{20-16} = rs; 24 let Inst{15-0} = imm; 25 } 26 27 class POOL32I_ADD_IMM_FM_MMR6<bits<5> funct> { 28 bits<5> rs; 29 bits<16> imm; 30 31 bits<32> Inst; 32 33 let Inst{31-26} = 0b010000; 34 let Inst{25-21} = funct; 35 let Inst{20-16} = rs; 36 let Inst{15-0} = imm; 37 } 38 39 class POOL32S_EXTBITS_FM_MMR6<bits<6> funct> { 40 bits<5> rt; 41 bits<5> rs; 42 bits<5> size; 43 bits<5> pos; 44 45 bits<32> Inst; 46 47 let Inst{31-26} = 0b010110; 48 let Inst{25-21} = rt; 49 let Inst{20-16} = rs; 50 let Inst{15-11} = size; 51 let Inst{10-6} = pos; 52 let Inst{5-0} = funct; 53 } 54 55 class POOL32S_DALIGN_FM_MMR6 { 56 bits<5> rs; 57 bits<5> rt; 58 bits<5> rd; 59 bits<3> bp; 60 61 bits<32> Inst; 62 63 let Inst{31-26} = 0b010110; 64 let Inst{25-21} = rs; 65 let Inst{20-16} = rt; 66 let Inst{15-11} = rd; 67 let Inst{10-8} = bp; 68 let Inst{7-6} = 0b00; 69 let Inst{5-0} = 0b011100; 70 } 71 72 class POOL32A_DIVMOD_FM_MMR6<string instr_asm, bits<9> funct> 73 : MMR6Arch<instr_asm> { 74 bits<5> rd; 75 bits<5> rs; 76 bits<5> rt; 77 78 bits<32> Inst; 79 80 let Inst{31-26} = 0b010110; 81 let Inst{25-21} = rd; 82 let Inst{20-16} = rs; 83 let Inst{15-11} = rt; 84 let Inst{10-9} = 0b00; 85 let Inst{8-0} = funct; 86 } 87
