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      1 //=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file describes Mips64r6 instructions.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 // Notes about removals/changes from MIPS32r6:
     15 // Reencoded: dclo, dclz
     16 
     17 //===----------------------------------------------------------------------===//
     18 //
     19 // Instruction Encodings
     20 //
     21 //===----------------------------------------------------------------------===//
     22 
     23 class DALIGN_ENC  : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
     24 class DAUI_ENC    : DAUI_FM;
     25 class DAHI_ENC    : REGIMM_FM<OPCODE5_DAHI>;
     26 class DATI_ENC    : REGIMM_FM<OPCODE5_DATI>;
     27 class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
     28 class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
     29 class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
     30 class DDIV_ENC    : SPECIAL_3R_FM<0b00010, 0b011110>;
     31 class DDIVU_ENC   : SPECIAL_3R_FM<0b00010, 0b011111>;
     32 class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>;
     33 class DMOD_ENC    : SPECIAL_3R_FM<0b00011, 0b011110>;
     34 class DMODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011111>;
     35 class DMUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011100>;
     36 class DMUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011101>;
     37 class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
     38 class DMULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011101>;
     39 class LDPC_ENC    : PCREL18_FM<OPCODE3_LDPC>;
     40 class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
     41 class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
     42 
     43 //===----------------------------------------------------------------------===//
     44 //
     45 // Instruction Descriptions
     46 //
     47 //===----------------------------------------------------------------------===//
     48 
     49 class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
     50   dag OutOperandList = (outs GPROpnd:$rs);
     51   dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
     52   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
     53   string Constraints = "$rs = $rt";
     54 }
     55 
     56 class DALIGN_DESC  : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
     57 class DAHI_DESC    : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>;
     58 class DATI_DESC    : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>;
     59 class DAUI_DESC    : AUI_DESC_BASE<"daui", GPR64Opnd>;
     60 class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
     61 class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd>;
     62 class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>;
     63 class DDIV_DESC    : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
     64 class DDIVU_DESC   : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
     65 class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1>;
     66 class DMOD_DESC    : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>;
     67 class DMODU_DESC   : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, urem>;
     68 class DMUH_DESC    : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, mulhs>;
     69 class DMUHU_DESC   : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>;
     70 class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, mul>;
     71 class DMULU_DESC   : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
     72 class LDPC_DESC    : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
     73 class LLD_R6_DESC   : LL_R6_DESC_BASE<"lld", GPR64Opnd>;
     74 class SCD_R6_DESC   : SC_R6_DESC_BASE<"scd", GPR64Opnd>;
     75 class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
     76 class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
     77 
     78 //===----------------------------------------------------------------------===//
     79 //
     80 // Instruction Definitions
     81 //
     82 //===----------------------------------------------------------------------===//
     83 
     84 let AdditionalPredicates = [NotInMicroMips] in {
     85   def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
     86   def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
     87   def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
     88   def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
     89 }
     90 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
     91 def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
     92 def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
     93 def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
     94 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
     95 def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
     96 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
     97 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
     98 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
     99 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
    100 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
    101 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
    102 def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
    103 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
    104 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
    105 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
    106   def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
    107   def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
    108 }
    109 
    110 //===----------------------------------------------------------------------===//
    111 //
    112 // Instruction Aliases
    113 //
    114 //===----------------------------------------------------------------------===//
    115 
    116 def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
    117 
    118 //===----------------------------------------------------------------------===//
    119 //
    120 // Patterns and Pseudo Instructions
    121 //
    122 //===----------------------------------------------------------------------===//
    123 
    124 // i64 selects
    125 def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
    126               (OR64 (SELNEZ64 i64:$t, i64:$cond),
    127                     (SELEQZ64 i64:$f, i64:$cond))>,
    128               ISA_MIPS64R6;
    129 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
    130               (OR64 (SELEQZ64 i64:$t, i64:$cond),
    131                     (SELNEZ64 i64:$f, i64:$cond))>,
    132               ISA_MIPS64R6;
    133 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
    134               (OR64 (SELNEZ64 i64:$t, i64:$cond),
    135                     (SELEQZ64 i64:$f, i64:$cond))>,
    136               ISA_MIPS64R6;
    137 def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
    138               (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
    139                     (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
    140               ISA_MIPS64R6;
    141 def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
    142               (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
    143                     (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
    144               ISA_MIPS64R6;
    145 def : MipsPat<
    146   (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
    147   (OR64 (SELEQZ64 i64:$t,
    148                   (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
    149                                  sub_32)),
    150         (SELNEZ64 i64:$f,
    151                   (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
    152                                  sub_32)))>,
    153   ISA_MIPS64R6;
    154 def : MipsPat<
    155   (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
    156   (OR64 (SELEQZ64 i64:$t,
    157                   (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
    158                                  sub_32)),
    159         (SELNEZ64 i64:$f,
    160                   (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
    161                                  sub_32)))>,
    162   ISA_MIPS64R6;
    163 
    164 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
    165               (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
    166 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
    167               (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
    168 def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
    169               (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
    170 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
    171               (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
    172 
    173 // i64 selects from an i32 comparison
    174 // One complicating factor here is that bits 32-63 of an i32 are undefined.
    175 // FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
    176 //        This would allow us to remove the sign-extensions here.
    177 def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
    178               (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
    179                     (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
    180               ISA_MIPS64R6;
    181 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
    182               (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
    183                     (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
    184               ISA_MIPS64R6;
    185 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
    186               (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
    187                     (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
    188               ISA_MIPS64R6;
    189 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
    190               (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
    191                                                       immZExt16:$imm))),
    192                     (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
    193                                                       immZExt16:$imm))))>,
    194               ISA_MIPS64R6;
    195 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
    196               (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
    197                                                       immZExt16:$imm))),
    198                     (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
    199                                                       immZExt16:$imm))))>,
    200               ISA_MIPS64R6;
    201 
    202 def : MipsPat<(select i32:$cond, i64:$t, immz),
    203               (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
    204               ISA_MIPS64R6;
    205 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
    206               (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
    207               ISA_MIPS64R6;
    208 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
    209               (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
    210               ISA_MIPS64R6;
    211 def : MipsPat<(select i32:$cond, immz, i64:$f),
    212               (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
    213               ISA_MIPS64R6;
    214 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
    215               (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
    216               ISA_MIPS64R6;
    217 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
    218               (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
    219               ISA_MIPS64R6;
    220