1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 class DspMMRel; 11 12 def Dsp2MicroMips : InstrMapping { 13 let FilterClass = "DspMMRel"; 14 // Instructions with the same BaseOpcode and isNVStore values form a row. 15 let RowFields = ["BaseOpcode"]; 16 // Instructions with the same predicate sense form a column. 17 let ColFields = ["Arch"]; 18 // The key column is the unpredicated instructions. 19 let KeyCol = ["dsp"]; 20 // Value columns are PredSense=true and PredSense=false 21 let ValueCols = [["dsp"], ["mmdsp"]]; 22 } 23 24 def HasDSP : Predicate<"Subtarget->hasDSP()">, 25 AssemblerPredicate<"FeatureDSP">; 26 def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">, 27 AssemblerPredicate<"FeatureDSPR2">; 28 def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">, 29 AssemblerPredicate<"FeatureDSPR3">; 30 31 class ISA_DSPR2 { 32 list<Predicate> InsnPredicates = [HasDSPR2]; 33 } 34 35 // Fields. 36 class Field6<bits<6> val> { 37 bits<6> V = val; 38 } 39 40 def SPECIAL3_OPCODE : Field6<0b011111>; 41 def REGIMM_OPCODE : Field6<0b000001>; 42 43 class DSPInst<string opstr = ""> 44 : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl { 45 let InsnPredicates = [HasDSP]; 46 string BaseOpcode = opstr; 47 string Arch = "dsp"; 48 } 49 50 class PseudoDSP<dag outs, dag ins, list<dag> pattern, 51 InstrItinClass itin = IIPseudo> 52 : MipsPseudo<outs, ins, pattern, itin>, PredicateControl { 53 let InsnPredicates = [HasDSP]; 54 } 55 56 class DSPInstAlias<string Asm, dag Result, bit Emit = 0b1> 57 : InstAlias<Asm, Result, Emit>, PredicateControl { 58 let InsnPredicates = [HasDSP]; 59 } 60 61 // ADDU.QB sub-class format. 62 class ADDU_QB_FMT<bits<5> op> : DSPInst { 63 bits<5> rd; 64 bits<5> rs; 65 bits<5> rt; 66 67 let Opcode = SPECIAL3_OPCODE.V; 68 69 let Inst{25-21} = rs; 70 let Inst{20-16} = rt; 71 let Inst{15-11} = rd; 72 let Inst{10-6} = op; 73 let Inst{5-0} = 0b010000; 74 } 75 76 class RADDU_W_QB_FMT<bits<5> op> : DSPInst { 77 bits<5> rd; 78 bits<5> rs; 79 80 let Opcode = SPECIAL3_OPCODE.V; 81 82 let Inst{25-21} = rs; 83 let Inst{20-16} = 0; 84 let Inst{15-11} = rd; 85 let Inst{10-6} = op; 86 let Inst{5-0} = 0b010000; 87 } 88 89 // CMPU.EQ.QB sub-class format. 90 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst { 91 bits<5> rs; 92 bits<5> rt; 93 94 let Opcode = SPECIAL3_OPCODE.V; 95 96 let Inst{25-21} = rs; 97 let Inst{20-16} = rt; 98 let Inst{15-11} = 0; 99 let Inst{10-6} = op; 100 let Inst{5-0} = 0b010001; 101 } 102 103 class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst { 104 bits<5> rs; 105 bits<5> rt; 106 bits<5> rd; 107 108 let Opcode = SPECIAL3_OPCODE.V; 109 110 let Inst{25-21} = rs; 111 let Inst{20-16} = rt; 112 let Inst{15-11} = rd; 113 let Inst{10-6} = op; 114 let Inst{5-0} = 0b010001; 115 } 116 117 class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst { 118 bits<5> rs; 119 bits<5> rt; 120 bits<5> sa; 121 122 let Opcode = SPECIAL3_OPCODE.V; 123 124 let Inst{25-21} = rs; 125 let Inst{20-16} = rt; 126 let Inst{15-11} = sa; 127 let Inst{10-6} = op; 128 let Inst{5-0} = 0b010001; 129 } 130 131 // ABSQ_S.PH sub-class format. 132 class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst { 133 bits<5> rd; 134 bits<5> rt; 135 136 let Opcode = SPECIAL3_OPCODE.V; 137 138 let Inst{25-21} = 0; 139 let Inst{20-16} = rt; 140 let Inst{15-11} = rd; 141 let Inst{10-6} = op; 142 let Inst{5-0} = 0b010010; 143 } 144 145 146 class REPL_FMT<bits<5> op> : DSPInst { 147 bits<5> rd; 148 bits<10> imm; 149 150 let Opcode = SPECIAL3_OPCODE.V; 151 152 let Inst{25-16} = imm; 153 let Inst{15-11} = rd; 154 let Inst{10-6} = op; 155 let Inst{5-0} = 0b010010; 156 } 157 158 // SHLL.QB sub-class format. 159 class SHLL_QB_FMT<bits<5> op> : DSPInst { 160 bits<5> rd; 161 bits<5> rt; 162 bits<5> rs_sa; 163 164 let Opcode = SPECIAL3_OPCODE.V; 165 166 let Inst{25-21} = rs_sa; 167 let Inst{20-16} = rt; 168 let Inst{15-11} = rd; 169 let Inst{10-6} = op; 170 let Inst{5-0} = 0b010011; 171 } 172 173 // LX sub-class format. 174 class LX_FMT<bits<5> op> : DSPInst { 175 bits<5> rd; 176 bits<5> base; 177 bits<5> index; 178 179 let Opcode = SPECIAL3_OPCODE.V; 180 181 let Inst{25-21} = base; 182 let Inst{20-16} = index; 183 let Inst{15-11} = rd; 184 let Inst{10-6} = op; 185 let Inst{5-0} = 0b001010; 186 } 187 188 // ADDUH.QB sub-class format. 189 class ADDUH_QB_FMT<bits<5> op> : DSPInst { 190 bits<5> rd; 191 bits<5> rs; 192 bits<5> rt; 193 194 let Opcode = SPECIAL3_OPCODE.V; 195 196 let Inst{25-21} = rs; 197 let Inst{20-16} = rt; 198 let Inst{15-11} = rd; 199 let Inst{10-6} = op; 200 let Inst{5-0} = 0b011000; 201 } 202 203 // APPEND sub-class format. 204 class APPEND_FMT<bits<5> op> : DSPInst { 205 bits<5> rt; 206 bits<5> rs; 207 bits<5> sa; 208 209 let Opcode = SPECIAL3_OPCODE.V; 210 211 let Inst{25-21} = rs; 212 let Inst{20-16} = rt; 213 let Inst{15-11} = sa; 214 let Inst{10-6} = op; 215 let Inst{5-0} = 0b110001; 216 } 217 218 // DPA.W.PH sub-class format. 219 class DPA_W_PH_FMT<bits<5> op> : DSPInst { 220 bits<2> ac; 221 bits<5> rs; 222 bits<5> rt; 223 224 let Opcode = SPECIAL3_OPCODE.V; 225 226 let Inst{25-21} = rs; 227 let Inst{20-16} = rt; 228 let Inst{15-13} = 0; 229 let Inst{12-11} = ac; 230 let Inst{10-6} = op; 231 let Inst{5-0} = 0b110000; 232 } 233 234 // MULT sub-class format. 235 class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst { 236 bits<2> ac; 237 bits<5> rs; 238 bits<5> rt; 239 240 let Opcode = opcode; 241 242 let Inst{25-21} = rs; 243 let Inst{20-16} = rt; 244 let Inst{15-13} = 0; 245 let Inst{12-11} = ac; 246 let Inst{10-6} = 0; 247 let Inst{5-0} = funct; 248 } 249 250 // MFHI sub-class format. 251 class MFHI_FMT<bits<6> funct> : DSPInst { 252 bits<5> rd; 253 bits<2> ac; 254 255 let Inst{31-26} = 0; 256 let Inst{25-23} = 0; 257 let Inst{22-21} = ac; 258 let Inst{20-16} = 0; 259 let Inst{15-11} = rd; 260 let Inst{10-6} = 0; 261 let Inst{5-0} = funct; 262 } 263 264 // MTHI sub-class format. 265 class MTHI_FMT<bits<6> funct> : DSPInst { 266 bits<5> rs; 267 bits<2> ac; 268 269 let Inst{31-26} = 0; 270 let Inst{25-21} = rs; 271 let Inst{20-13} = 0; 272 let Inst{12-11} = ac; 273 let Inst{10-6} = 0; 274 let Inst{5-0} = funct; 275 } 276 277 // EXTR.W sub-class format (type 1). 278 class EXTR_W_TY1_FMT<bits<5> op> : DSPInst { 279 bits<5> rt; 280 bits<2> ac; 281 bits<5> shift_rs; 282 283 let Opcode = SPECIAL3_OPCODE.V; 284 285 let Inst{25-21} = shift_rs; 286 let Inst{20-16} = rt; 287 let Inst{15-13} = 0; 288 let Inst{12-11} = ac; 289 let Inst{10-6} = op; 290 let Inst{5-0} = 0b111000; 291 } 292 293 // SHILO sub-class format. 294 class SHILO_R1_FMT<bits<5> op> : DSPInst { 295 bits<2> ac; 296 bits<6> shift; 297 298 let Opcode = SPECIAL3_OPCODE.V; 299 300 let Inst{25-20} = shift; 301 let Inst{19-13} = 0; 302 let Inst{12-11} = ac; 303 let Inst{10-6} = op; 304 let Inst{5-0} = 0b111000; 305 } 306 307 class SHILO_R2_FMT<bits<5> op> : DSPInst { 308 bits<2> ac; 309 bits<5> rs; 310 311 let Opcode = SPECIAL3_OPCODE.V; 312 313 let Inst{25-21} = rs; 314 let Inst{20-13} = 0; 315 let Inst{12-11} = ac; 316 let Inst{10-6} = op; 317 let Inst{5-0} = 0b111000; 318 } 319 320 class RDDSP_FMT<bits<5> op> : DSPInst { 321 bits<5> rd; 322 bits<10> mask; 323 324 let Opcode = SPECIAL3_OPCODE.V; 325 326 let Inst{25-16} = mask; 327 let Inst{15-11} = rd; 328 let Inst{10-6} = op; 329 let Inst{5-0} = 0b111000; 330 } 331 332 class WRDSP_FMT<bits<5> op> : DSPInst { 333 bits<5> rs; 334 bits<10> mask; 335 336 let Opcode = SPECIAL3_OPCODE.V; 337 338 let Inst{25-21} = rs; 339 let Inst{20-11} = mask; 340 let Inst{10-6} = op; 341 let Inst{5-0} = 0b111000; 342 } 343 344 class BPOSGE32_FMT<bits<5> op> : DSPInst { 345 bits<16> offset; 346 347 let Opcode = REGIMM_OPCODE.V; 348 349 let Inst{25-21} = 0; 350 let Inst{20-16} = op; 351 let Inst{15-0} = offset; 352 } 353 354 // INSV sub-class format. 355 class INSV_FMT<bits<6> op> : DSPInst { 356 bits<5> rt; 357 bits<5> rs; 358 359 let Opcode = SPECIAL3_OPCODE.V; 360 361 let Inst{25-21} = rs; 362 let Inst{20-16} = rt; 363 let Inst{15-6} = 0; 364 let Inst{5-0} = op; 365 } 366
