1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips DSP ASE instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // ImmLeaf 15 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>; 16 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>; 17 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>; 18 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>; 19 def immZExt7 : ImmLeaf<i32, [{return isUInt<7>(Imm);}]>; 20 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>; 21 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>; 22 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>; 23 24 // Mips-specific dsp nodes 25 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 26 SDTCisVT<2, untyped>]>; 27 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 28 SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>; 29 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 30 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 31 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 32 SDTCisVT<2, i32>]>; 33 34 class MipsDSPBase<string Opc, SDTypeProfile Prof> : 35 SDNode<!strconcat("MipsISD::", Opc), Prof>; 36 37 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> : 38 SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>; 39 40 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>; 41 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>; 42 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>; 43 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>; 44 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>; 45 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>; 46 47 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>; 48 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>; 49 50 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>; 51 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>; 52 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>; 53 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>; 54 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>; 55 56 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>; 57 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>; 58 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>; 59 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>; 60 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>; 61 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>; 62 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>; 63 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>; 64 65 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>; 66 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>; 67 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>; 68 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>; 69 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>; 70 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>; 71 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>; 72 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>; 73 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>; 74 75 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>; 76 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>; 77 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>; 78 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>; 79 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>; 80 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>; 81 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>; 82 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>; 83 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>; 84 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>; 85 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>; 86 87 // Flags. 88 class Uses<list<Register> Regs> { 89 list<Register> Uses = Regs; 90 } 91 92 class Defs<list<Register> Regs> { 93 list<Register> Defs = Regs; 94 } 95 96 // Instruction encoding. 97 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>; 98 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>; 99 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>; 100 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>; 101 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>; 102 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>; 103 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>; 104 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>; 105 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>; 106 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>; 107 class ADDSC_ENC : ADDU_QB_FMT<0b10000>; 108 class ADDWC_ENC : ADDU_QB_FMT<0b10001>; 109 class MODSUB_ENC : ADDU_QB_FMT<0b10010>; 110 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>; 111 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>; 112 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>; 113 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>; 114 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>; 115 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>; 116 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>; 117 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>; 118 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>; 119 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>; 120 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>; 121 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>; 122 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>; 123 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>; 124 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>; 125 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>; 126 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>; 127 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>; 128 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>; 129 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>; 130 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>; 131 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>; 132 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>; 133 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>; 134 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>; 135 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>; 136 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>; 137 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>; 138 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>; 139 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>; 140 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>; 141 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>; 142 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>; 143 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>; 144 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>; 145 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>; 146 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>; 147 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>; 148 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>; 149 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>; 150 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>; 151 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>; 152 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>; 153 class MFHI_ENC : MFHI_FMT<0b010000>; 154 class MFLO_ENC : MFHI_FMT<0b010010>; 155 class MTHI_ENC : MTHI_FMT<0b010001>; 156 class MTLO_ENC : MTHI_FMT<0b010011>; 157 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>; 158 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>; 159 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>; 160 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>; 161 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>; 162 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>; 163 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>; 164 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>; 165 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>; 166 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>; 167 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>; 168 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>; 169 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>; 170 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>; 171 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>; 172 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>; 173 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>; 174 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>; 175 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>; 176 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>; 177 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>; 178 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>; 179 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>; 180 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>; 181 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>; 182 class REPL_QB_ENC : REPL_FMT<0b00010>; 183 class REPL_PH_ENC : REPL_FMT<0b01010>; 184 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>; 185 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>; 186 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>; 187 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>; 188 class LWX_ENC : LX_FMT<0b00000>; 189 class LHX_ENC : LX_FMT<0b00100>; 190 class LBUX_ENC : LX_FMT<0b00110>; 191 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>; 192 class INSV_ENC : INSV_FMT<0b001100>; 193 194 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>; 195 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>; 196 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>; 197 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>; 198 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>; 199 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>; 200 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>; 201 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>; 202 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>; 203 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>; 204 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>; 205 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>; 206 class SHILO_ENC : SHILO_R1_FMT<0b11010>; 207 class SHILOV_ENC : SHILO_R2_FMT<0b11011>; 208 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>; 209 210 class RDDSP_ENC : RDDSP_FMT<0b10010>; 211 class WRDSP_ENC : WRDSP_FMT<0b10011>; 212 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>; 213 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>; 214 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>; 215 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>; 216 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>; 217 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>; 218 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>; 219 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>; 220 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>; 221 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>; 222 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>; 223 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>; 224 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>; 225 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>; 226 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>; 227 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>; 228 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>; 229 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>; 230 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>; 231 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>; 232 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>; 233 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>; 234 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>; 235 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>; 236 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>; 237 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>; 238 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>; 239 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>; 240 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>; 241 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>; 242 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>; 243 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>; 244 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>; 245 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>; 246 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>; 247 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>; 248 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>; 249 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>; 250 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>; 251 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>; 252 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>; 253 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>; 254 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>; 255 class APPEND_ENC : APPEND_FMT<0b00000>; 256 class BALIGN_ENC : APPEND_FMT<0b10000>; 257 class PREPEND_ENC : APPEND_FMT<0b00001>; 258 259 // Instruction desc. 260 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 261 InstrItinClass itin, RegisterOperand ROD, 262 RegisterOperand ROS, RegisterOperand ROT = ROS> { 263 dag OutOperandList = (outs ROD:$rd); 264 dag InOperandList = (ins ROS:$rs, ROT:$rt); 265 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 266 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))]; 267 InstrItinClass Itinerary = itin; 268 string BaseOpcode = instr_asm; 269 } 270 271 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 272 InstrItinClass itin, RegisterOperand ROD, 273 RegisterOperand ROS = ROD> { 274 dag OutOperandList = (outs ROD:$rd); 275 dag InOperandList = (ins ROS:$rs); 276 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 277 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))]; 278 InstrItinClass Itinerary = itin; 279 string BaseOpcode = instr_asm; 280 } 281 282 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 283 InstrItinClass itin, RegisterOperand ROS, 284 RegisterOperand ROT = ROS> { 285 dag OutOperandList = (outs); 286 dag InOperandList = (ins ROS:$rs, ROT:$rt); 287 string AsmString = !strconcat(instr_asm, "\t$rs, $rt"); 288 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)]; 289 InstrItinClass Itinerary = itin; 290 } 291 292 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 293 InstrItinClass itin, RegisterOperand ROD, 294 RegisterOperand ROS, RegisterOperand ROT = ROS> { 295 dag OutOperandList = (outs ROD:$rd); 296 dag InOperandList = (ins ROS:$rs, ROT:$rt); 297 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 298 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))]; 299 InstrItinClass Itinerary = itin; 300 string BaseOpcode = instr_asm; 301 } 302 303 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 304 InstrItinClass itin, RegisterOperand ROT, 305 RegisterOperand ROS = ROT> { 306 dag OutOperandList = (outs ROT:$rt); 307 dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src); 308 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 309 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))]; 310 InstrItinClass Itinerary = itin; 311 string Constraints = "$src = $rt"; 312 string BaseOpcode = instr_asm; 313 } 314 315 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 316 InstrItinClass itin, RegisterOperand ROD, 317 RegisterOperand ROT = ROD> { 318 dag OutOperandList = (outs ROD:$rd); 319 dag InOperandList = (ins ROT:$rt); 320 string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); 321 list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))]; 322 InstrItinClass Itinerary = itin; 323 string BaseOpcode = instr_asm; 324 } 325 326 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 327 ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> { 328 dag OutOperandList = (outs RO:$rd); 329 dag InOperandList = (ins uimm16:$imm); 330 string AsmString = !strconcat(instr_asm, "\t$rd, $imm"); 331 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))]; 332 InstrItinClass Itinerary = itin; 333 string BaseOpcode = instr_asm; 334 } 335 336 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 337 InstrItinClass itin, RegisterOperand RO> { 338 dag OutOperandList = (outs RO:$rd); 339 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa); 340 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); 341 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))]; 342 InstrItinClass Itinerary = itin; 343 string BaseOpcode = instr_asm; 344 } 345 346 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 347 SDPatternOperator ImmPat, InstrItinClass itin, 348 RegisterOperand RO, Operand ImmOpnd> { 349 dag OutOperandList = (outs RO:$rd); 350 dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa); 351 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); 352 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))]; 353 InstrItinClass Itinerary = itin; 354 bit hasSideEffects = 1; 355 string BaseOpcode = instr_asm; 356 } 357 358 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 359 InstrItinClass itin> { 360 dag OutOperandList = (outs GPR32Opnd:$rd); 361 dag InOperandList = (ins PtrRC:$base, PtrRC:$index); 362 string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})"); 363 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))]; 364 InstrItinClass Itinerary = itin; 365 bit mayLoad = 1; 366 string BaseOpcode = instr_asm; 367 } 368 369 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 370 InstrItinClass itin, RegisterOperand ROD, 371 RegisterOperand ROS = ROD, RegisterOperand ROT = ROD> { 372 dag OutOperandList = (outs ROD:$rd); 373 dag InOperandList = (ins ROS:$rs, ROT:$rt); 374 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 375 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))]; 376 InstrItinClass Itinerary = itin; 377 string BaseOpcode = instr_asm; 378 } 379 380 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 381 Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> { 382 dag OutOperandList = (outs GPR32Opnd:$rt); 383 dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src); 384 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 385 list<dag> Pattern = [(set GPR32Opnd:$rt, 386 (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))]; 387 InstrItinClass Itinerary = itin; 388 string Constraints = "$src = $rt"; 389 string BaseOpcode = instr_asm; 390 } 391 392 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 393 InstrItinClass itin> { 394 dag OutOperandList = (outs GPR32Opnd:$rt); 395 dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs); 396 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 397 InstrItinClass Itinerary = itin; 398 string BaseOpcode = instr_asm; 399 } 400 401 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 402 InstrItinClass itin> { 403 dag OutOperandList = (outs GPR32Opnd:$rt); 404 dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs); 405 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 406 InstrItinClass Itinerary = itin; 407 string BaseOpcode = instr_asm; 408 } 409 410 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 411 dag OutOperandList = (outs ACC64DSPOpnd:$ac); 412 dag InOperandList = (ins simm6:$shift, ACC64DSPOpnd:$acin); 413 string AsmString = !strconcat(instr_asm, "\t$ac, $shift"); 414 list<dag> Pattern = [(set ACC64DSPOpnd:$ac, 415 (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))]; 416 string Constraints = "$acin = $ac"; 417 string BaseOpcode = instr_asm; 418 } 419 420 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 421 dag OutOperandList = (outs ACC64DSPOpnd:$ac); 422 dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin); 423 string AsmString = !strconcat(instr_asm, "\t$ac, $rs"); 424 list<dag> Pattern = [(set ACC64DSPOpnd:$ac, 425 (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))]; 426 string Constraints = "$acin = $ac"; 427 string BaseOpcode = instr_asm; 428 } 429 430 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 431 dag OutOperandList = (outs ACC64DSPOpnd:$ac); 432 dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin); 433 string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); 434 list<dag> Pattern = [(set ACC64DSPOpnd:$ac, 435 (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))]; 436 string Constraints = "$acin = $ac"; 437 string BaseOpcode = instr_asm; 438 } 439 440 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 441 InstrItinClass itin> { 442 dag OutOperandList = (outs GPR32Opnd:$rd); 443 dag InOperandList = (ins uimm16:$mask); 444 string AsmString = !strconcat(instr_asm, "\t$rd, $mask"); 445 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))]; 446 InstrItinClass Itinerary = itin; 447 string BaseOpcode = instr_asm; 448 } 449 450 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 451 InstrItinClass itin> { 452 dag OutOperandList = (outs); 453 dag InOperandList = (ins GPR32Opnd:$rs, uimm10:$mask); 454 string AsmString = !strconcat(instr_asm, "\t$rs, $mask"); 455 list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)]; 456 InstrItinClass Itinerary = itin; 457 string BaseOpcode = instr_asm; 458 } 459 460 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 461 dag OutOperandList = (outs ACC64DSPOpnd:$ac); 462 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin); 463 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 464 list<dag> Pattern = [(set ACC64DSPOpnd:$ac, 465 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))]; 466 string Constraints = "$acin = $ac"; 467 string BaseOpcode = instr_asm; 468 } 469 470 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 471 InstrItinClass itin> { 472 dag OutOperandList = (outs ACC64DSPOpnd:$ac); 473 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt); 474 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 475 list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))]; 476 InstrItinClass Itinerary = itin; 477 bit isCommutable = 1; 478 string BaseOpcode = instr_asm; 479 } 480 481 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 482 InstrItinClass itin> { 483 dag OutOperandList = (outs ACC64DSPOpnd:$ac); 484 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin); 485 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 486 list<dag> Pattern = [(set ACC64DSPOpnd:$ac, 487 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))]; 488 InstrItinClass Itinerary = itin; 489 string Constraints = "$acin = $ac"; 490 string BaseOpcode = instr_asm; 491 } 492 493 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode, 494 InstrItinClass itin> { 495 dag OutOperandList = (outs GPR32Opnd:$rd); 496 dag InOperandList = (ins RO:$ac); 497 string AsmString = !strconcat(instr_asm, "\t$rd, $ac"); 498 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))]; 499 InstrItinClass Itinerary = itin; 500 string BaseOpcode = instr_asm; 501 } 502 503 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> { 504 dag OutOperandList = (outs RO:$ac); 505 dag InOperandList = (ins GPR32Opnd:$rs); 506 string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); 507 InstrItinClass Itinerary = itin; 508 string BaseOpcode = instr_asm; 509 } 510 511 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> : 512 MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> { 513 bit usesCustomInserter = 1; 514 } 515 516 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> { 517 dag OutOperandList = (outs); 518 dag InOperandList = (ins brtarget:$offset); 519 string AsmString = !strconcat(instr_asm, "\t$offset"); 520 InstrItinClass Itinerary = itin; 521 bit isBranch = 1; 522 bit isTerminator = 1; 523 bit hasDelaySlot = 1; 524 } 525 526 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 527 InstrItinClass itin> { 528 dag OutOperandList = (outs GPR32Opnd:$rt); 529 dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs); 530 string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); 531 list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))]; 532 InstrItinClass Itinerary = itin; 533 string Constraints = "$src = $rt"; 534 string BaseOpcode = instr_asm; 535 } 536 537 //===----------------------------------------------------------------------===// 538 // MIPS DSP Rev 1 539 //===----------------------------------------------------------------------===// 540 541 // Addition/subtraction 542 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary, 543 DSPROpnd, DSPROpnd>, IsCommutable, 544 Defs<[DSPOutFlag20]>; 545 546 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb, 547 NoItinerary, DSPROpnd, DSPROpnd>, 548 IsCommutable, Defs<[DSPOutFlag20]>; 549 550 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary, 551 DSPROpnd, DSPROpnd>, 552 Defs<[DSPOutFlag20]>; 553 554 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb, 555 NoItinerary, DSPROpnd, DSPROpnd>, 556 Defs<[DSPOutFlag20]>; 557 558 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary, 559 DSPROpnd, DSPROpnd>, IsCommutable, 560 Defs<[DSPOutFlag20]>; 561 562 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph, 563 NoItinerary, DSPROpnd, DSPROpnd>, 564 IsCommutable, Defs<[DSPOutFlag20]>; 565 566 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary, 567 DSPROpnd, DSPROpnd>, 568 Defs<[DSPOutFlag20]>; 569 570 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph, 571 NoItinerary, DSPROpnd, DSPROpnd>, 572 Defs<[DSPOutFlag20]>; 573 574 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w, 575 NoItinerary, GPR32Opnd, GPR32Opnd>, 576 IsCommutable, Defs<[DSPOutFlag20]>; 577 578 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w, 579 NoItinerary, GPR32Opnd, GPR32Opnd>, 580 Defs<[DSPOutFlag20]>; 581 582 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary, 583 GPR32Opnd, GPR32Opnd>, IsCommutable, 584 Defs<[DSPCarry]>; 585 586 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary, 587 GPR32Opnd, GPR32Opnd>, 588 IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>; 589 590 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary, 591 GPR32Opnd, GPR32Opnd>; 592 593 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb, 594 NoItinerary, GPR32Opnd, DSPROpnd>; 595 596 // Absolute value 597 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph, 598 NoItinerary, DSPROpnd>, 599 Defs<[DSPOutFlag20]>; 600 601 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w, 602 NoItinerary, GPR32Opnd>, 603 Defs<[DSPOutFlag20]>; 604 605 // Precision reduce/expand 606 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph", 607 int_mips_precrq_qb_ph, 608 NoItinerary, DSPROpnd, DSPROpnd>; 609 610 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w", 611 int_mips_precrq_ph_w, 612 NoItinerary, DSPROpnd, GPR32Opnd>; 613 614 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w", 615 int_mips_precrq_rs_ph_w, 616 NoItinerary, DSPROpnd, 617 GPR32Opnd>, 618 Defs<[DSPOutFlag22]>; 619 620 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph", 621 int_mips_precrqu_s_qb_ph, 622 NoItinerary, DSPROpnd, 623 DSPROpnd>, 624 Defs<[DSPOutFlag22]>; 625 626 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl", 627 int_mips_preceq_w_phl, 628 NoItinerary, GPR32Opnd, DSPROpnd>; 629 630 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr", 631 int_mips_preceq_w_phr, 632 NoItinerary, GPR32Opnd, DSPROpnd>; 633 634 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl", 635 int_mips_precequ_ph_qbl, 636 NoItinerary, DSPROpnd>; 637 638 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr", 639 int_mips_precequ_ph_qbr, 640 NoItinerary, DSPROpnd>; 641 642 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla", 643 int_mips_precequ_ph_qbla, 644 NoItinerary, DSPROpnd>; 645 646 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra", 647 int_mips_precequ_ph_qbra, 648 NoItinerary, DSPROpnd>; 649 650 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl", 651 int_mips_preceu_ph_qbl, 652 NoItinerary, DSPROpnd>; 653 654 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr", 655 int_mips_preceu_ph_qbr, 656 NoItinerary, DSPROpnd>; 657 658 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla", 659 int_mips_preceu_ph_qbla, 660 NoItinerary, DSPROpnd>; 661 662 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra", 663 int_mips_preceu_ph_qbra, 664 NoItinerary, DSPROpnd>; 665 666 // Shift 667 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3, 668 NoItinerary, DSPROpnd, uimm3>, 669 Defs<[DSPOutFlag22]>; 670 671 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb, 672 NoItinerary, DSPROpnd>, 673 Defs<[DSPOutFlag22]>; 674 675 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3, 676 NoItinerary, DSPROpnd, uimm3>; 677 678 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb, 679 NoItinerary, DSPROpnd>; 680 681 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4, 682 NoItinerary, DSPROpnd, uimm4>, 683 Defs<[DSPOutFlag22]>; 684 685 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph, 686 NoItinerary, DSPROpnd>, 687 Defs<[DSPOutFlag22]>; 688 689 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph, 690 immZExt4, NoItinerary, DSPROpnd, 691 uimm4>, 692 Defs<[DSPOutFlag22]>; 693 694 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph, 695 NoItinerary, DSPROpnd>, 696 Defs<[DSPOutFlag22]>; 697 698 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4, 699 NoItinerary, DSPROpnd, uimm4>; 700 701 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph, 702 NoItinerary, DSPROpnd>; 703 704 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph, 705 immZExt4, NoItinerary, DSPROpnd, 706 uimm4>; 707 708 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph, 709 NoItinerary, DSPROpnd>; 710 711 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w, 712 immZExt5, NoItinerary, GPR32Opnd, 713 uimm5>, 714 Defs<[DSPOutFlag22]>; 715 716 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w, 717 NoItinerary, GPR32Opnd>, 718 Defs<[DSPOutFlag22]>; 719 720 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w, 721 immZExt5, NoItinerary, GPR32Opnd, 722 uimm5>; 723 724 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w, 725 NoItinerary, GPR32Opnd>; 726 727 // Multiplication 728 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl", 729 int_mips_muleu_s_ph_qbl, 730 NoItinerary, DSPROpnd, DSPROpnd>, 731 Defs<[DSPOutFlag21]>; 732 733 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr", 734 int_mips_muleu_s_ph_qbr, 735 NoItinerary, DSPROpnd, DSPROpnd>, 736 Defs<[DSPOutFlag21]>; 737 738 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl", 739 int_mips_muleq_s_w_phl, 740 NoItinerary, GPR32Opnd, DSPROpnd>, 741 IsCommutable, Defs<[DSPOutFlag21]>; 742 743 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr", 744 int_mips_muleq_s_w_phr, 745 NoItinerary, GPR32Opnd, DSPROpnd>, 746 IsCommutable, Defs<[DSPOutFlag21]>; 747 748 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph, 749 NoItinerary, DSPROpnd, DSPROpnd>, 750 IsCommutable, Defs<[DSPOutFlag21]>; 751 752 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph", 753 MipsMULSAQ_S_W_PH>, 754 Defs<[DSPOutFlag16_19]>; 755 756 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>, 757 Defs<[DSPOutFlag16_19]>; 758 759 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>, 760 Defs<[DSPOutFlag16_19]>; 761 762 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>, 763 Defs<[DSPOutFlag16_19]>; 764 765 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>, 766 Defs<[DSPOutFlag16_19]>; 767 768 // Move from/to hi/lo. 769 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>; 770 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>; 771 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>; 772 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>; 773 774 // Dot product with accumulate/subtract 775 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>; 776 777 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>; 778 779 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>; 780 781 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>; 782 783 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>, 784 Defs<[DSPOutFlag16_19]>; 785 786 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>, 787 Defs<[DSPOutFlag16_19]>; 788 789 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>, 790 Defs<[DSPOutFlag16_19]>; 791 792 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>, 793 Defs<[DSPOutFlag16_19]>; 794 795 class MULT_DSP_DESC : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>; 796 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>; 797 class MADD_DSP_DESC : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>; 798 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>; 799 class MSUB_DSP_DESC : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>; 800 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>; 801 802 // Comparison 803 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb", 804 int_mips_cmpu_eq_qb, NoItinerary, 805 DSPROpnd>, 806 IsCommutable, Defs<[DSPCCond]>; 807 808 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb", 809 int_mips_cmpu_lt_qb, NoItinerary, 810 DSPROpnd>, Defs<[DSPCCond]>; 811 812 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb", 813 int_mips_cmpu_le_qb, NoItinerary, 814 DSPROpnd>, Defs<[DSPCCond]>; 815 816 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb", 817 int_mips_cmpgu_eq_qb, 818 NoItinerary, GPR32Opnd, DSPROpnd>, 819 IsCommutable; 820 821 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb", 822 int_mips_cmpgu_lt_qb, 823 NoItinerary, GPR32Opnd, DSPROpnd>; 824 825 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb", 826 int_mips_cmpgu_le_qb, 827 NoItinerary, GPR32Opnd, DSPROpnd>; 828 829 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph, 830 NoItinerary, DSPROpnd>, 831 IsCommutable, Defs<[DSPCCond]>; 832 833 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph, 834 NoItinerary, DSPROpnd>, 835 Defs<[DSPCCond]>; 836 837 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph, 838 NoItinerary, DSPROpnd>, 839 Defs<[DSPCCond]>; 840 841 // Misc 842 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev, 843 NoItinerary, GPR32Opnd>; 844 845 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph, 846 NoItinerary, DSPROpnd, DSPROpnd>; 847 848 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8, 849 NoItinerary, DSPROpnd>; 850 851 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10, 852 NoItinerary, DSPROpnd>; 853 854 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb, 855 NoItinerary, DSPROpnd, GPR32Opnd>; 856 857 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph, 858 NoItinerary, DSPROpnd, GPR32Opnd>; 859 860 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb, 861 NoItinerary, DSPROpnd, DSPROpnd>, 862 Uses<[DSPCCond]>; 863 864 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph, 865 NoItinerary, DSPROpnd, DSPROpnd>, 866 Uses<[DSPCCond]>; 867 868 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>; 869 870 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>; 871 872 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>; 873 874 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>; 875 876 // Extr 877 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>, 878 Uses<[DSPPos]>, Defs<[DSPEFI]>; 879 880 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>, 881 Uses<[DSPPos]>, Defs<[DSPEFI]>; 882 883 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>, 884 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>; 885 886 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP, 887 NoItinerary>, 888 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>; 889 890 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>, 891 Defs<[DSPOutFlag23]>; 892 893 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W, 894 NoItinerary>, Defs<[DSPOutFlag23]>; 895 896 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W, 897 NoItinerary>, 898 Defs<[DSPOutFlag23]>; 899 900 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W, 901 NoItinerary>, 902 Defs<[DSPOutFlag23]>; 903 904 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W, 905 NoItinerary>, 906 Defs<[DSPOutFlag23]>; 907 908 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W, 909 NoItinerary>, 910 Defs<[DSPOutFlag23]>; 911 912 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H, 913 NoItinerary>, 914 Defs<[DSPOutFlag23]>; 915 916 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H, 917 NoItinerary>, 918 Defs<[DSPOutFlag23]>; 919 920 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>; 921 922 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>; 923 924 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>; 925 926 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>; 927 928 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>; 929 930 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>, 931 Uses<[DSPPos, DSPSCount]>; 932 933 //===----------------------------------------------------------------------===// 934 // MIPS DSP Rev 2 935 // Addition/subtraction 936 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary, 937 DSPROpnd, DSPROpnd>, IsCommutable, 938 Defs<[DSPOutFlag20]>; 939 940 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph, 941 NoItinerary, DSPROpnd, DSPROpnd>, 942 IsCommutable, Defs<[DSPOutFlag20]>; 943 944 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary, 945 DSPROpnd, DSPROpnd>, 946 Defs<[DSPOutFlag20]>; 947 948 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph, 949 NoItinerary, DSPROpnd, DSPROpnd>, 950 Defs<[DSPOutFlag20]>; 951 952 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb, 953 NoItinerary, DSPROpnd>, IsCommutable; 954 955 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb, 956 NoItinerary, DSPROpnd>, IsCommutable; 957 958 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb, 959 NoItinerary, DSPROpnd>; 960 961 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb, 962 NoItinerary, DSPROpnd>; 963 964 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph, 965 NoItinerary, DSPROpnd>, IsCommutable; 966 967 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph, 968 NoItinerary, DSPROpnd>, IsCommutable; 969 970 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph, 971 NoItinerary, DSPROpnd>; 972 973 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph, 974 NoItinerary, DSPROpnd>; 975 976 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w, 977 NoItinerary, GPR32Opnd>, IsCommutable; 978 979 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w, 980 NoItinerary, GPR32Opnd>, IsCommutable; 981 982 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w, 983 NoItinerary, GPR32Opnd>; 984 985 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w, 986 NoItinerary, GPR32Opnd>; 987 988 // Comparison 989 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb", 990 int_mips_cmpgdu_eq_qb, 991 NoItinerary, GPR32Opnd, DSPROpnd>, 992 IsCommutable, Defs<[DSPCCond]>; 993 994 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb", 995 int_mips_cmpgdu_lt_qb, 996 NoItinerary, GPR32Opnd, DSPROpnd>, 997 Defs<[DSPCCond]>; 998 999 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb", 1000 int_mips_cmpgdu_le_qb, 1001 NoItinerary, GPR32Opnd, DSPROpnd>, 1002 Defs<[DSPCCond]>; 1003 1004 // Absolute 1005 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb, 1006 NoItinerary, DSPROpnd>, 1007 Defs<[DSPOutFlag20]>; 1008 1009 // Multiplication 1010 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary, 1011 DSPROpnd>, IsCommutable, 1012 Defs<[DSPOutFlag21]>; 1013 1014 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph, 1015 NoItinerary, DSPROpnd>, IsCommutable, 1016 Defs<[DSPOutFlag21]>; 1017 1018 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w, 1019 NoItinerary, GPR32Opnd>, IsCommutable, 1020 Defs<[DSPOutFlag21]>; 1021 1022 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w, 1023 NoItinerary, GPR32Opnd>, IsCommutable, 1024 Defs<[DSPOutFlag21]>; 1025 1026 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph, 1027 NoItinerary, DSPROpnd, DSPROpnd>, 1028 IsCommutable, Defs<[DSPOutFlag21]>; 1029 1030 // Dot product with accumulate/subtract 1031 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>; 1032 1033 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>; 1034 1035 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>, 1036 Defs<[DSPOutFlag16_19]>; 1037 1038 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph", 1039 MipsDPAQX_SA_W_PH>, 1040 Defs<[DSPOutFlag16_19]>; 1041 1042 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>; 1043 1044 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>; 1045 1046 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>, 1047 Defs<[DSPOutFlag16_19]>; 1048 1049 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph", 1050 MipsDPSQX_SA_W_PH>, 1051 Defs<[DSPOutFlag16_19]>; 1052 1053 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>; 1054 1055 // Precision reduce/expand 1056 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph", 1057 int_mips_precr_qb_ph, 1058 NoItinerary, DSPROpnd, DSPROpnd>; 1059 1060 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w", 1061 int_mips_precr_sra_ph_w, 1062 NoItinerary, DSPROpnd, 1063 GPR32Opnd>; 1064 1065 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w", 1066 int_mips_precr_sra_r_ph_w, 1067 NoItinerary, DSPROpnd, 1068 GPR32Opnd>; 1069 1070 // Shift 1071 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3, 1072 NoItinerary, DSPROpnd, uimm3>; 1073 1074 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb, 1075 NoItinerary, DSPROpnd>; 1076 1077 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb, 1078 immZExt3, NoItinerary, DSPROpnd, 1079 uimm3>; 1080 1081 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb, 1082 NoItinerary, DSPROpnd>; 1083 1084 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4, 1085 NoItinerary, DSPROpnd, uimm4>; 1086 1087 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph, 1088 NoItinerary, DSPROpnd>; 1089 1090 // Misc 1091 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, immZExt5, 1092 NoItinerary>; 1093 1094 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, immZExt2, 1095 NoItinerary>; 1096 1097 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5, 1098 immZExt5, NoItinerary>; 1099 1100 // Pseudos. 1101 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, 1102 NoItinerary>, Uses<[DSPPos]>; 1103 1104 // Instruction defs. 1105 // MIPS DSP Rev 1 1106 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC; 1107 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC; 1108 def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC; 1109 def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC; 1110 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC; 1111 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC; 1112 def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC; 1113 def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC; 1114 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC; 1115 def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC; 1116 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC; 1117 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC; 1118 def MODSUB : MODSUB_ENC, MODSUB_DESC; 1119 def RADDU_W_QB : DspMMRel, RADDU_W_QB_ENC, RADDU_W_QB_DESC; 1120 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC; 1121 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC; 1122 def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC; 1123 def PRECRQ_PH_W : DspMMRel, PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC; 1124 def PRECRQ_RS_PH_W : DspMMRel, PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC; 1125 def PRECRQU_S_QB_PH : DspMMRel, PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC; 1126 def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC; 1127 def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC; 1128 def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC; 1129 def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC; 1130 def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC; 1131 def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC; 1132 def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC; 1133 def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC; 1134 def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC; 1135 def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC; 1136 def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC; 1137 def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC; 1138 def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC; 1139 def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC; 1140 def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC; 1141 def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC; 1142 def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC; 1143 def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC; 1144 def SHRA_PH : DspMMRel, SHRA_PH_ENC, SHRA_PH_DESC; 1145 def SHRAV_PH : DspMMRel, SHRAV_PH_ENC, SHRAV_PH_DESC; 1146 def SHRA_R_PH : DspMMRel, SHRA_R_PH_ENC, SHRA_R_PH_DESC; 1147 def SHRAV_R_PH : DspMMRel, SHRAV_R_PH_ENC, SHRAV_R_PH_DESC; 1148 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC; 1149 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC; 1150 def SHRA_R_W : DspMMRel, SHRA_R_W_ENC, SHRA_R_W_DESC; 1151 def SHRAV_R_W : DspMMRel, SHRAV_R_W_ENC, SHRAV_R_W_DESC; 1152 def MULEU_S_PH_QBL : DspMMRel, MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC; 1153 def MULEU_S_PH_QBR : DspMMRel, MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC; 1154 def MULEQ_S_W_PHL : DspMMRel, MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC; 1155 def MULEQ_S_W_PHR : DspMMRel, MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC; 1156 def MULQ_RS_PH : DspMMRel, MULQ_RS_PH_ENC, MULQ_RS_PH_DESC; 1157 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC; 1158 def MAQ_S_W_PHL : DspMMRel, MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC; 1159 def MAQ_S_W_PHR : DspMMRel, MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC; 1160 def MAQ_SA_W_PHL : DspMMRel, MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC; 1161 def MAQ_SA_W_PHR : DspMMRel, MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC; 1162 def MFHI_DSP : DspMMRel, MFHI_ENC, MFHI_DESC; 1163 def MFLO_DSP : DspMMRel, MFLO_ENC, MFLO_DESC; 1164 def MTHI_DSP : DspMMRel, MTHI_ENC, MTHI_DESC; 1165 def MTLO_DSP : DspMMRel, MTLO_ENC, MTLO_DESC; 1166 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC; 1167 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC; 1168 def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC; 1169 def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC; 1170 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC; 1171 def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC; 1172 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC; 1173 def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC; 1174 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC; 1175 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC; 1176 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC; 1177 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC; 1178 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC; 1179 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC; 1180 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC; 1181 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC; 1182 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC; 1183 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC; 1184 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC; 1185 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC; 1186 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC; 1187 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC; 1188 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC; 1189 def BITREV : BITREV_ENC, BITREV_DESC; 1190 def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC; 1191 def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC; 1192 def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC; 1193 def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC; 1194 def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC; 1195 def PICK_QB : DspMMRel, PICK_QB_ENC, PICK_QB_DESC; 1196 def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC; 1197 def LWX : DspMMRel, LWX_ENC, LWX_DESC; 1198 def LHX : DspMMRel, LHX_ENC, LHX_DESC; 1199 def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC; 1200 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC; 1201 def INSV : DspMMRel, INSV_ENC, INSV_DESC; 1202 def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC; 1203 def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC; 1204 def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC; 1205 def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC; 1206 def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC; 1207 def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC; 1208 def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC; 1209 def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC; 1210 def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC; 1211 def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC; 1212 def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC; 1213 def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC; 1214 def SHILO : DspMMRel, SHILO_ENC, SHILO_DESC; 1215 def SHILOV : DspMMRel, SHILOV_ENC, SHILOV_DESC; 1216 def MTHLIP : DspMMRel, MTHLIP_ENC, MTHLIP_DESC; 1217 def RDDSP : DspMMRel, RDDSP_ENC, RDDSP_DESC; 1218 let AdditionalPredicates = [NotInMicroMips] in { 1219 def WRDSP : WRDSP_ENC, WRDSP_DESC; 1220 } 1221 1222 // MIPS DSP Rev 2 1223 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC, ISA_DSPR2; 1224 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2; 1225 def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2; 1226 def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2; 1227 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2; 1228 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2; 1229 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2; 1230 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2; 1231 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2; 1232 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2; 1233 def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC, ISA_DSPR2; 1234 def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC, ISA_DSPR2; 1235 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC, ISA_DSPR2; 1236 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC, ISA_DSPR2; 1237 def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC, ISA_DSPR2; 1238 def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC, ISA_DSPR2; 1239 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC, ISA_DSPR2; 1240 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC, ISA_DSPR2; 1241 def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC, ISA_DSPR2; 1242 def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC, ISA_DSPR2; 1243 def MUL_PH : DspMMRel, MUL_PH_ENC, MUL_PH_DESC, ISA_DSPR2; 1244 def MUL_S_PH : DspMMRel, MUL_S_PH_ENC, MUL_S_PH_DESC, ISA_DSPR2; 1245 def MULQ_S_W : DspMMRel, MULQ_S_W_ENC, MULQ_S_W_DESC, ISA_DSPR2; 1246 def MULQ_RS_W : DspMMRel, MULQ_RS_W_ENC, MULQ_RS_W_DESC, ISA_DSPR2; 1247 def MULQ_S_PH : DspMMRel, MULQ_S_PH_ENC, MULQ_S_PH_DESC, ISA_DSPR2; 1248 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC, ISA_DSPR2; 1249 def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC, ISA_DSPR2; 1250 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC, ISA_DSPR2; 1251 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC, ISA_DSPR2; 1252 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC, ISA_DSPR2; 1253 def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC, ISA_DSPR2; 1254 def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC, ISA_DSPR2; 1255 def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC, ISA_DSPR2; 1256 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC, ISA_DSPR2; 1257 def PRECR_QB_PH : DspMMRel, PRECR_QB_PH_ENC, PRECR_QB_PH_DESC, ISA_DSPR2; 1258 def PRECR_SRA_PH_W : DspMMRel, PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC, ISA_DSPR2; 1259 def PRECR_SRA_R_PH_W : DspMMRel, PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC, ISA_DSPR2; 1260 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC, ISA_DSPR2; 1261 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC, ISA_DSPR2; 1262 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC, ISA_DSPR2; 1263 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2; 1264 def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2; 1265 def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2; 1266 def APPEND : APPEND_ENC, APPEND_DESC, ISA_DSPR2; 1267 def BALIGN : BALIGN_ENC, BALIGN_DESC, ISA_DSPR2; 1268 def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2; 1269 1270 // Pseudos. 1271 let isPseudo = 1, isCodeGenOnly = 1 in { 1272 // Pseudo instructions for loading and storing accumulator registers. 1273 def LOAD_ACC64DSP : Load<"", ACC64DSPOpnd>; 1274 def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>; 1275 1276 // Pseudos for loading and storing ccond field of DSP control register. 1277 def LOAD_CCOND_DSP : Load<"load_ccond_dsp", DSPCC>; 1278 def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>; 1279 } 1280 1281 // Pseudo CMP and PICK instructions. 1282 class PseudoCMP<Instruction RealInst> : 1283 PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>, 1284 PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects; 1285 1286 class PseudoPICK<Instruction RealInst> : 1287 PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>, 1288 PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>, 1289 NeverHasSideEffects; 1290 1291 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>; 1292 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>; 1293 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>; 1294 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>; 1295 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>; 1296 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>; 1297 1298 def PseudoPICK_PH : PseudoPICK<PICK_PH>; 1299 def PseudoPICK_QB : PseudoPICK<PICK_QB>; 1300 1301 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>; 1302 1303 // Patterns. 1304 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> : 1305 Pat<pattern, result>, Requires<[pred]>; 1306 1307 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, 1308 RegisterClass SrcRC> : 1309 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))), 1310 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>; 1311 1312 def : BitconvertPat<i32, v2i16, GPR32, DSPR>; 1313 def : BitconvertPat<i32, v4i8, GPR32, DSPR>; 1314 def : BitconvertPat<v2i16, i32, DSPR, GPR32>; 1315 def : BitconvertPat<v4i8, i32, DSPR, GPR32>; 1316 1317 def : DSPPat<(v2i16 (load addr:$a)), 1318 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>; 1319 def : DSPPat<(v4i8 (load addr:$a)), 1320 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>; 1321 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a), 1322 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>; 1323 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a), 1324 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>; 1325 1326 // Binary operations. 1327 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node, 1328 Predicate Pred = HasDSP> : 1329 DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>; 1330 1331 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>; 1332 def : DSPBinPat<ADDQ_PH, v2i16, add>; 1333 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>; 1334 def : DSPBinPat<SUBQ_PH, v2i16, sub>; 1335 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>; 1336 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>; 1337 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>; 1338 def : DSPBinPat<ADDU_QB, v4i8, add>; 1339 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>; 1340 def : DSPBinPat<SUBU_QB, v4i8, sub>; 1341 def : DSPBinPat<ADDSC, i32, int_mips_addsc>; 1342 def : DSPBinPat<ADDSC, i32, addc>; 1343 def : DSPBinPat<ADDWC, i32, int_mips_addwc>; 1344 def : DSPBinPat<ADDWC, i32, adde>; 1345 1346 // Shift immediate patterns. 1347 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node, 1348 SDPatternOperator Imm, Predicate Pred = HasDSP> : 1349 DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>; 1350 1351 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>; 1352 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>; 1353 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>; 1354 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>; 1355 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>; 1356 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>; 1357 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>; 1358 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>; 1359 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>; 1360 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>; 1361 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>; 1362 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>; 1363 1364 // SETCC/SELECT_CC patterns. 1365 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy, 1366 CondCode CC> : 1367 DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)), 1368 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), 1369 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)), 1370 (ValTy ZERO)))>; 1371 1372 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy, 1373 CondCode CC> : 1374 DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)), 1375 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), 1376 (ValTy ZERO), 1377 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>; 1378 1379 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy, 1380 CondCode CC> : 1381 DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)), 1382 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>; 1383 1384 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy, 1385 CondCode CC> : 1386 DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)), 1387 (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>; 1388 1389 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>; 1390 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>; 1391 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>; 1392 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>; 1393 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>; 1394 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>; 1395 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>; 1396 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>; 1397 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>; 1398 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>; 1399 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>; 1400 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>; 1401 1402 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>; 1403 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>; 1404 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>; 1405 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>; 1406 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>; 1407 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>; 1408 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>; 1409 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>; 1410 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>; 1411 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>; 1412 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>; 1413 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>; 1414 1415 // Extr patterns. 1416 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> : 1417 DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)), 1418 (Instr ACC64DSP:$ac, GPR32:$rs)>; 1419 1420 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> : 1421 DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)), 1422 (Instr ACC64DSP:$ac, immZExt5:$shift)>; 1423 1424 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>; 1425 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>; 1426 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>; 1427 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>; 1428 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>; 1429 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>; 1430 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>; 1431 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>; 1432 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>; 1433 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>; 1434 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>; 1435 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>; 1436 1437 // Indexed load patterns. 1438 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> : 1439 DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))), 1440 (Instr i32:$base, i32:$index)>; 1441 1442 let AddedComplexity = 20 in { 1443 def : IndexedLoadPat<zextloadi8, LBUX>; 1444 def : IndexedLoadPat<sextloadi16, LHX>; 1445 def : IndexedLoadPat<load, LWX>; 1446 } 1447 1448 // Instruction alias. 1449 let AdditionalPredicates = [NotInMicroMips] in { 1450 def : DSPInstAlias<"wrdsp $rt", (WRDSP GPR32Opnd:$rt, 0x1F), 1>; 1451 } 1452
