1 //===- MipsEVAInstrInfo.td - EVA ASE instructions -*- tablegen ------------*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips EVA ASE instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // 16 // Instruction encodings 17 // 18 //===----------------------------------------------------------------------===// 19 20 // Memory Load/Store EVA encodings 21 class LBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LBE>; 22 class LBuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LBuE>; 23 class LHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LHE>; 24 class LHuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LHuE>; 25 class LWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWE>; 26 27 class SBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SBE>; 28 class SHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SHE>; 29 class SWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWE>; 30 31 // load/store left/right EVA encodings 32 class LWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWLE>; 33 class LWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWRE>; 34 class SWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWLE>; 35 class SWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWRE>; 36 37 // Load-linked EVA, Store-conditional EVA encodings 38 class LLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LLE>; 39 class SCE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SCE>; 40 41 class TLBINV_ENC : TLB_FM<OPCODE6_TLBINV>; 42 class TLBINVF_ENC : TLB_FM<OPCODE6_TLBINVF>; 43 44 class CACHEE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_CACHEE>; 45 class PREFE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_PREFE>; 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Instruction descriptions 50 // 51 //===----------------------------------------------------------------------===// 52 53 // Memory Load/Store EVA descriptions 54 class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 55 dag OutOperandList = (outs GPROpnd:$rt); 56 dag InOperandList = (ins mem_simm9:$addr); 57 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 58 list<dag> Pattern = []; 59 string DecoderMethod = "DecodeMemEVA"; 60 bit canFoldAsLoad = 1; 61 bit mayLoad = 1; 62 } 63 64 class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd>; 65 class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd>; 66 class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd>; 67 class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd>; 68 class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd>; 69 70 class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 71 SDPatternOperator OpNode = null_frag> { 72 dag OutOperandList = (outs); 73 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 74 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 75 list<dag> Pattern = []; 76 string DecoderMethod = "DecodeMemEVA"; 77 bit mayStore = 1; 78 } 79 80 class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd>; 81 class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd>; 82 class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd>; 83 84 // Load/Store Left/Right EVA descriptions 85 class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 86 dag OutOperandList = (outs GPROpnd:$rt); 87 dag InOperandList = (ins mem_simm9:$addr, GPROpnd:$src); 88 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 89 list<dag> Pattern = []; 90 string DecoderMethod = "DecodeMemEVA"; 91 string Constraints = "$src = $rt"; 92 bit canFoldAsLoad = 1; 93 } 94 95 class LWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwle", GPR32Opnd>; 96 class LWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwre", GPR32Opnd>; 97 98 class STORE_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 99 dag OutOperandList = (outs); 100 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 101 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 102 list<dag> Pattern = []; 103 string DecoderMethod = "DecodeMemEVA"; 104 } 105 106 class SWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swle", GPR32Opnd>; 107 class SWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swre", GPR32Opnd>; 108 109 // Load-linked EVA, Store-conditional EVA descriptions 110 class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 111 dag OutOperandList = (outs GPROpnd:$rt); 112 dag InOperandList = (ins mem_simm9:$addr); 113 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 114 list<dag> Pattern = []; 115 bit mayLoad = 1; 116 string DecoderMethod = "DecodeMemEVA"; 117 } 118 119 class LLE_DESC : LLE_DESC_BASE<"lle", GPR32Opnd>; 120 121 class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 122 dag OutOperandList = (outs GPROpnd:$dst); 123 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 124 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 125 list<dag> Pattern = []; 126 bit mayStore = 1; 127 string Constraints = "$rt = $dst"; 128 string DecoderMethod = "DecodeMemEVA"; 129 } 130 131 class SCE_DESC : SCE_DESC_BASE<"sce", GPR32Opnd>; 132 133 class TLB_DESC_BASE<string instr_asm> { 134 dag OutOperandList = (outs); 135 dag InOperandList = (ins); 136 string AsmString = instr_asm; 137 list<dag> Pattern = []; 138 } 139 140 class TLBINV_DESC : TLB_DESC_BASE<"tlbinv">; 141 class TLBINVF_DESC : TLB_DESC_BASE<"tlbinvf">; 142 143 class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd> { 144 dag OutOperandList = (outs); 145 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); 146 string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); 147 list<dag> Pattern = []; 148 string DecoderMethod = "DecodeCacheeOp_CacheOpR6"; 149 } 150 151 class CACHEE_DESC : CACHEE_DESC_BASE<"cachee", mem>; 152 class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem>; 153 154 //===----------------------------------------------------------------------===// 155 // 156 // Instruction definitions 157 // 158 //===----------------------------------------------------------------------===// 159 160 /// Load and Store EVA Instructions 161 def LBE : LBE_ENC, LBE_DESC, INSN_EVA; 162 def LBuE : LBuE_ENC, LBuE_DESC, INSN_EVA; 163 def LHE : LHE_ENC, LHE_DESC, INSN_EVA; 164 def LHuE : LHuE_ENC, LHuE_DESC, INSN_EVA; 165 let AdditionalPredicates = [NotInMicroMips] in { 166 def LWE : LWE_ENC, LWE_DESC, INSN_EVA; 167 } 168 def SBE : SBE_ENC, SBE_DESC, INSN_EVA; 169 def SHE : SHE_ENC, SHE_DESC, INSN_EVA; 170 let AdditionalPredicates = [NotInMicroMips] in { 171 def SWE : SWE_ENC, SWE_DESC, INSN_EVA; 172 } 173 174 /// load/store left/right EVA 175 let AdditionalPredicates = [NotInMicroMips] in { 176 def LWLE : LWLE_ENC, LWLE_DESC, INSN_EVA_NOT_32R6_64R6; 177 def LWRE : LWRE_ENC, LWRE_DESC, INSN_EVA_NOT_32R6_64R6; 178 def SWLE : SWLE_ENC, SWLE_DESC, INSN_EVA_NOT_32R6_64R6; 179 def SWRE : SWRE_ENC, SWRE_DESC, INSN_EVA_NOT_32R6_64R6; 180 } 181 182 /// Load-linked EVA, Store-conditional EVA 183 let AdditionalPredicates = [NotInMicroMips] in { 184 def LLE : LLE_ENC, LLE_DESC, INSN_EVA; 185 def SCE : SCE_ENC, SCE_DESC, INSN_EVA; 186 } 187 188 def TLBINV : TLBINV_ENC, TLBINV_DESC, INSN_EVA; 189 def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA; 190 191 def CACHEE : CACHEE_ENC, CACHEE_DESC, INSN_EVA; 192 def PREFE : PREFE_ENC, PREFE_DESC, INSN_EVA; 193
