1 //===-- MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Functional units across Mips chips sets. Based on GCC/Mips backend files. 12 //===----------------------------------------------------------------------===// 13 def ALU : FuncUnit; 14 def IMULDIV : FuncUnit; 15 16 //===----------------------------------------------------------------------===// 17 // Instruction Itinerary classes used for Mips 18 //===----------------------------------------------------------------------===// 19 // IIM16Alu is a placeholder class for most MIPS16 instructions. 20 def IIM16Alu : InstrItinClass; 21 def IIPseudo : InstrItinClass; 22 23 def II_ABS : InstrItinClass; 24 def II_ADDI : InstrItinClass; 25 def II_ADDIU : InstrItinClass; 26 def II_ADDU : InstrItinClass; 27 def II_ADD_D : InstrItinClass; 28 def II_ADD_S : InstrItinClass; 29 def II_AND : InstrItinClass; 30 def II_ANDI : InstrItinClass; 31 def II_B : InstrItinClass; 32 def II_BADDU : InstrItinClass; 33 def II_BBIT : InstrItinClass; // bbit[01], bbit[01]32 34 def II_BC : InstrItinClass; 35 def II_BC1F : InstrItinClass; 36 def II_BC1FL : InstrItinClass; 37 def II_BC1T : InstrItinClass; 38 def II_BC1TL : InstrItinClass; 39 def II_BCC : InstrItinClass; // beq and bne 40 def II_BCCZ : InstrItinClass; // b[gl][et]z 41 def II_BCCZAL : InstrItinClass; // bgezal and bltzal 42 def II_BCCZALS : InstrItinClass; // bgezals and bltzals 43 def II_BCCZC : InstrItinClass; // beqzc, bnezc 44 def II_CEIL : InstrItinClass; 45 def II_CFC1 : InstrItinClass; 46 def II_CLO : InstrItinClass; 47 def II_CLZ : InstrItinClass; 48 def II_CTC1 : InstrItinClass; 49 def II_CVT : InstrItinClass; 50 def II_C_CC_D : InstrItinClass; // Any c.<cc>.d instruction 51 def II_C_CC_S : InstrItinClass; // Any c.<cc>.s instruction 52 def II_DADDIU : InstrItinClass; 53 def II_DADDU : InstrItinClass; 54 def II_DADD : InstrItinClass; 55 def II_DDIV : InstrItinClass; 56 def II_DDIVU : InstrItinClass; 57 def II_DIV : InstrItinClass; 58 def II_DIVU : InstrItinClass; 59 def II_DIV_D : InstrItinClass; 60 def II_DIV_S : InstrItinClass; 61 def II_DMFC1 : InstrItinClass; 62 def II_DMTC1 : InstrItinClass; 63 def II_DMUL : InstrItinClass; 64 def II_DMULT : InstrItinClass; 65 def II_DMULTU : InstrItinClass; 66 def II_DROTR : InstrItinClass; 67 def II_DROTR32 : InstrItinClass; 68 def II_DROTRV : InstrItinClass; 69 def II_DSLL : InstrItinClass; 70 def II_DSLL32 : InstrItinClass; 71 def II_DSLLV : InstrItinClass; 72 def II_DSRA : InstrItinClass; 73 def II_DSRA32 : InstrItinClass; 74 def II_DSRAV : InstrItinClass; 75 def II_DSRL : InstrItinClass; 76 def II_DSRL32 : InstrItinClass; 77 def II_DSRLV : InstrItinClass; 78 def II_DSUBU : InstrItinClass; 79 def II_DSUB : InstrItinClass; 80 def II_EXT : InstrItinClass; // Any EXT instruction 81 def II_FLOOR : InstrItinClass; 82 def II_INS : InstrItinClass; // Any INS instruction 83 def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo. 84 def II_J : InstrItinClass; 85 def II_JAL : InstrItinClass; 86 def II_JALR : InstrItinClass; 87 def II_JALRC : InstrItinClass; 88 def II_JALRS : InstrItinClass; 89 def II_JALS : InstrItinClass; 90 def II_JR : InstrItinClass; 91 def II_JRADDIUSP : InstrItinClass; 92 def II_JRC : InstrItinClass; 93 def II_ReturnPseudo : InstrItinClass; // Return pseudo. 94 def II_LB : InstrItinClass; 95 def II_LBE : InstrItinClass; 96 def II_LBU : InstrItinClass; 97 def II_LBUE : InstrItinClass; 98 def II_LD : InstrItinClass; 99 def II_LDC1 : InstrItinClass; 100 def II_LDL : InstrItinClass; 101 def II_LDR : InstrItinClass; 102 def II_LDXC1 : InstrItinClass; 103 def II_LH : InstrItinClass; 104 def II_LHE : InstrItinClass; 105 def II_LHU : InstrItinClass; 106 def II_LHUE : InstrItinClass; 107 def II_LUI : InstrItinClass; 108 def II_LUXC1 : InstrItinClass; 109 def II_LW : InstrItinClass; 110 def II_LWE : InstrItinClass; 111 def II_LWC1 : InstrItinClass; 112 def II_LWL : InstrItinClass; 113 def II_LWLE : InstrItinClass; 114 def II_LWR : InstrItinClass; 115 def II_LWRE : InstrItinClass; 116 def II_LWU : InstrItinClass; 117 def II_LWXC1 : InstrItinClass; 118 def II_MADD : InstrItinClass; 119 def II_MADDU : InstrItinClass; 120 def II_MADD_D : InstrItinClass; 121 def II_MADD_S : InstrItinClass; 122 def II_MFC1 : InstrItinClass; 123 def II_MFHC1 : InstrItinClass; 124 def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo 125 def II_MOVF : InstrItinClass; 126 def II_MOVF_D : InstrItinClass; 127 def II_MOVF_S : InstrItinClass; 128 def II_MOVN : InstrItinClass; 129 def II_MOVN_D : InstrItinClass; 130 def II_MOVN_S : InstrItinClass; 131 def II_MOVT : InstrItinClass; 132 def II_MOVT_D : InstrItinClass; 133 def II_MOVT_S : InstrItinClass; 134 def II_MOVZ : InstrItinClass; 135 def II_MOVZ_D : InstrItinClass; 136 def II_MOVZ_S : InstrItinClass; 137 def II_MOV_D : InstrItinClass; 138 def II_MOV_S : InstrItinClass; 139 def II_MSUB : InstrItinClass; 140 def II_MSUBU : InstrItinClass; 141 def II_MSUB_D : InstrItinClass; 142 def II_MSUB_S : InstrItinClass; 143 def II_MTC1 : InstrItinClass; 144 def II_MTHC1 : InstrItinClass; 145 def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo 146 def II_MUL : InstrItinClass; 147 def II_MULT : InstrItinClass; 148 def II_MULTU : InstrItinClass; 149 def II_MUL_D : InstrItinClass; 150 def II_MUL_S : InstrItinClass; 151 def II_NEG : InstrItinClass; 152 def II_NMADD_D : InstrItinClass; 153 def II_NMADD_S : InstrItinClass; 154 def II_NMSUB_D : InstrItinClass; 155 def II_NMSUB_S : InstrItinClass; 156 def II_NOR : InstrItinClass; 157 def II_OR : InstrItinClass; 158 def II_ORI : InstrItinClass; 159 def II_POP : InstrItinClass; 160 def II_RDHWR : InstrItinClass; 161 def II_RESTORE : InstrItinClass; 162 def II_ROTR : InstrItinClass; 163 def II_ROTRV : InstrItinClass; 164 def II_ROUND : InstrItinClass; 165 def II_SAVE : InstrItinClass; 166 def II_SB : InstrItinClass; 167 def II_SBE : InstrItinClass; 168 def II_SD : InstrItinClass; 169 def II_SDC1 : InstrItinClass; 170 def II_SDL : InstrItinClass; 171 def II_SDR : InstrItinClass; 172 def II_SDXC1 : InstrItinClass; 173 def II_SEB : InstrItinClass; 174 def II_SEH : InstrItinClass; 175 def II_SEQ_SNE : InstrItinClass; // seq and sne 176 def II_SEQI_SNEI : InstrItinClass; // seqi and snei 177 def II_SH : InstrItinClass; 178 def II_SHE : InstrItinClass; 179 def II_SLL : InstrItinClass; 180 def II_SLLV : InstrItinClass; 181 def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu 182 def II_SLT_SLTU : InstrItinClass; // slt and sltu 183 def II_SQRT_D : InstrItinClass; 184 def II_SQRT_S : InstrItinClass; 185 def II_SRA : InstrItinClass; 186 def II_SRAV : InstrItinClass; 187 def II_SRL : InstrItinClass; 188 def II_SRLV : InstrItinClass; 189 def II_SUBU : InstrItinClass; 190 def II_SUB_D : InstrItinClass; 191 def II_SUB_S : InstrItinClass; 192 def II_SUXC1 : InstrItinClass; 193 def II_SW : InstrItinClass; 194 def II_SWE : InstrItinClass; 195 def II_SWC1 : InstrItinClass; 196 def II_SWL : InstrItinClass; 197 def II_SWLE : InstrItinClass; 198 def II_SWR : InstrItinClass; 199 def II_SWRE : InstrItinClass; 200 def II_SWXC1 : InstrItinClass; 201 def II_TRUNC : InstrItinClass; 202 def II_WSBH : InstrItinClass; 203 def II_XOR : InstrItinClass; 204 def II_XORI : InstrItinClass; 205 206 //===----------------------------------------------------------------------===// 207 // Mips Generic instruction itineraries. 208 //===----------------------------------------------------------------------===// 209 def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ 210 InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>, 211 InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>, 212 InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>, 213 InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>, 214 InstrItinData<II_AND , [InstrStage<1, [ALU]>]>, 215 InstrItinData<II_BADDU , [InstrStage<1, [ALU]>]>, 216 InstrItinData<II_SLL , [InstrStage<1, [ALU]>]>, 217 InstrItinData<II_SRA , [InstrStage<1, [ALU]>]>, 218 InstrItinData<II_SRL , [InstrStage<1, [ALU]>]>, 219 InstrItinData<II_ROTR , [InstrStage<1, [ALU]>]>, 220 InstrItinData<II_SLLV , [InstrStage<1, [ALU]>]>, 221 InstrItinData<II_SRAV , [InstrStage<1, [ALU]>]>, 222 InstrItinData<II_SRLV , [InstrStage<1, [ALU]>]>, 223 InstrItinData<II_ROTRV , [InstrStage<1, [ALU]>]>, 224 InstrItinData<II_CLO , [InstrStage<1, [ALU]>]>, 225 InstrItinData<II_CLZ , [InstrStage<1, [ALU]>]>, 226 InstrItinData<II_DADDIU , [InstrStage<1, [ALU]>]>, 227 InstrItinData<II_DADDU , [InstrStage<1, [ALU]>]>, 228 InstrItinData<II_DADD , [InstrStage<1, [ALU]>]>, 229 InstrItinData<II_DSLL , [InstrStage<1, [ALU]>]>, 230 InstrItinData<II_DSRL , [InstrStage<1, [ALU]>]>, 231 InstrItinData<II_DSRA , [InstrStage<1, [ALU]>]>, 232 InstrItinData<II_DSLLV , [InstrStage<1, [ALU]>]>, 233 InstrItinData<II_DSRLV , [InstrStage<1, [ALU]>]>, 234 InstrItinData<II_DSRAV , [InstrStage<1, [ALU]>]>, 235 InstrItinData<II_DSUBU , [InstrStage<1, [ALU]>]>, 236 InstrItinData<II_DSUB , [InstrStage<1, [ALU]>]>, 237 InstrItinData<II_DROTR , [InstrStage<1, [ALU]>]>, 238 InstrItinData<II_DROTRV , [InstrStage<1, [ALU]>]>, 239 InstrItinData<II_EXT , [InstrStage<1, [ALU]>]>, 240 InstrItinData<II_INS , [InstrStage<1, [ALU]>]>, 241 InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>, 242 InstrItinData<II_MOVF , [InstrStage<1, [ALU]>]>, 243 InstrItinData<II_MOVN , [InstrStage<1, [ALU]>]>, 244 InstrItinData<II_MOVN_S , [InstrStage<1, [ALU]>]>, 245 InstrItinData<II_MOVN_D , [InstrStage<1, [ALU]>]>, 246 InstrItinData<II_MOVT , [InstrStage<1, [ALU]>]>, 247 InstrItinData<II_MOVZ , [InstrStage<1, [ALU]>]>, 248 InstrItinData<II_NOR , [InstrStage<1, [ALU]>]>, 249 InstrItinData<II_OR , [InstrStage<1, [ALU]>]>, 250 InstrItinData<II_POP , [InstrStage<1, [ALU]>]>, 251 InstrItinData<II_RDHWR , [InstrStage<1, [ALU]>]>, 252 InstrItinData<II_SUBU , [InstrStage<1, [ALU]>]>, 253 InstrItinData<II_XOR , [InstrStage<1, [ALU]>]>, 254 InstrItinData<II_ANDI , [InstrStage<1, [ALU]>]>, 255 InstrItinData<II_ORI , [InstrStage<1, [ALU]>]>, 256 InstrItinData<II_XORI , [InstrStage<1, [ALU]>]>, 257 InstrItinData<II_LB , [InstrStage<3, [ALU]>]>, 258 InstrItinData<II_LBU , [InstrStage<3, [ALU]>]>, 259 InstrItinData<II_LH , [InstrStage<3, [ALU]>]>, 260 InstrItinData<II_LHU , [InstrStage<3, [ALU]>]>, 261 InstrItinData<II_LW , [InstrStage<3, [ALU]>]>, 262 InstrItinData<II_LWL , [InstrStage<3, [ALU]>]>, 263 InstrItinData<II_LWR , [InstrStage<3, [ALU]>]>, 264 InstrItinData<II_LD , [InstrStage<3, [ALU]>]>, 265 InstrItinData<II_LDL , [InstrStage<3, [ALU]>]>, 266 InstrItinData<II_LDR , [InstrStage<3, [ALU]>]>, 267 InstrItinData<II_RESTORE , [InstrStage<3, [ALU]>]>, 268 InstrItinData<II_SB , [InstrStage<1, [ALU]>]>, 269 InstrItinData<II_SH , [InstrStage<1, [ALU]>]>, 270 InstrItinData<II_SW , [InstrStage<1, [ALU]>]>, 271 InstrItinData<II_SWL , [InstrStage<1, [ALU]>]>, 272 InstrItinData<II_SWR , [InstrStage<1, [ALU]>]>, 273 InstrItinData<II_SDL , [InstrStage<1, [ALU]>]>, 274 InstrItinData<II_SDR , [InstrStage<1, [ALU]>]>, 275 InstrItinData<II_SD , [InstrStage<1, [ALU]>]>, 276 InstrItinData<II_SAVE , [InstrStage<1, [ALU]>]>, 277 InstrItinData<II_SEQ_SNE , [InstrStage<1, [ALU]>]>, 278 InstrItinData<II_SEQI_SNEI , [InstrStage<1, [ALU]>]>, 279 InstrItinData<II_B , [InstrStage<1, [ALU]>]>, 280 InstrItinData<II_BBIT , [InstrStage<1, [ALU]>]>, 281 InstrItinData<II_BC , [InstrStage<1, [ALU]>]>, 282 InstrItinData<II_BC1F , [InstrStage<1, [ALU]>]>, 283 InstrItinData<II_BC1FL , [InstrStage<1, [ALU]>]>, 284 InstrItinData<II_BC1T , [InstrStage<1, [ALU]>]>, 285 InstrItinData<II_BC1TL , [InstrStage<1, [ALU]>]>, 286 InstrItinData<II_BCC , [InstrStage<1, [ALU]>]>, 287 InstrItinData<II_BCCZ , [InstrStage<1, [ALU]>]>, 288 InstrItinData<II_BCCZAL , [InstrStage<1, [ALU]>]>, 289 InstrItinData<II_BCCZALS , [InstrStage<1, [ALU]>]>, 290 InstrItinData<II_BCCZC , [InstrStage<1, [ALU]>]>, 291 InstrItinData<II_IndirectBranchPseudo, [InstrStage<1, [ALU]>]>, 292 InstrItinData<II_J , [InstrStage<1, [ALU]>]>, 293 InstrItinData<II_JAL , [InstrStage<1, [ALU]>]>, 294 InstrItinData<II_JALR , [InstrStage<1, [ALU]>]>, 295 InstrItinData<II_JALRC , [InstrStage<1, [ALU]>]>, 296 InstrItinData<II_JALRS , [InstrStage<1, [ALU]>]>, 297 InstrItinData<II_JALS , [InstrStage<1, [ALU]>]>, 298 InstrItinData<II_JR , [InstrStage<1, [ALU]>]>, 299 InstrItinData<II_JRADDIUSP , [InstrStage<1, [ALU]>]>, 300 InstrItinData<II_JRC , [InstrStage<1, [ALU]>]>, 301 InstrItinData<II_ReturnPseudo , [InstrStage<1, [ALU]>]>, 302 InstrItinData<II_DMUL , [InstrStage<17, [IMULDIV]>]>, 303 InstrItinData<II_DMULT , [InstrStage<17, [IMULDIV]>]>, 304 InstrItinData<II_DMULTU , [InstrStage<17, [IMULDIV]>]>, 305 InstrItinData<II_MADD , [InstrStage<17, [IMULDIV]>]>, 306 InstrItinData<II_MADDU , [InstrStage<17, [IMULDIV]>]>, 307 InstrItinData<II_MFHI_MFLO , [InstrStage<1, [IMULDIV]>]>, 308 InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>, 309 InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>, 310 InstrItinData<II_MTHI_MTLO , [InstrStage<1, [IMULDIV]>]>, 311 InstrItinData<II_MUL , [InstrStage<17, [IMULDIV]>]>, 312 InstrItinData<II_MULT , [InstrStage<17, [IMULDIV]>]>, 313 InstrItinData<II_MULTU , [InstrStage<17, [IMULDIV]>]>, 314 InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>, 315 InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>, 316 InstrItinData<II_DIV , [InstrStage<38, [IMULDIV]>]>, 317 InstrItinData<II_DIVU , [InstrStage<38, [IMULDIV]>]>, 318 InstrItinData<II_DDIV , [InstrStage<38, [IMULDIV]>]>, 319 InstrItinData<II_DDIVU , [InstrStage<38, [IMULDIV]>]>, 320 InstrItinData<II_CEIL , [InstrStage<1, [ALU]>]>, 321 InstrItinData<II_CVT , [InstrStage<1, [ALU]>]>, 322 InstrItinData<II_ABS , [InstrStage<1, [ALU]>]>, 323 InstrItinData<II_FLOOR , [InstrStage<1, [ALU]>]>, 324 InstrItinData<II_NEG , [InstrStage<1, [ALU]>]>, 325 InstrItinData<II_ROUND , [InstrStage<1, [ALU]>]>, 326 InstrItinData<II_TRUNC , [InstrStage<1, [ALU]>]>, 327 InstrItinData<II_MOV_D , [InstrStage<2, [ALU]>]>, 328 InstrItinData<II_MOV_S , [InstrStage<2, [ALU]>]>, 329 InstrItinData<II_CFC1 , [InstrStage<2, [ALU]>]>, 330 InstrItinData<II_CTC1 , [InstrStage<2, [ALU]>]>, 331 InstrItinData<II_MOVF_D , [InstrStage<2, [ALU]>]>, 332 InstrItinData<II_MOVF_S , [InstrStage<2, [ALU]>]>, 333 InstrItinData<II_MOVT_D , [InstrStage<2, [ALU]>]>, 334 InstrItinData<II_MOVT_S , [InstrStage<2, [ALU]>]>, 335 InstrItinData<II_MOVZ_D , [InstrStage<2, [ALU]>]>, 336 InstrItinData<II_MOVZ_S , [InstrStage<2, [ALU]>]>, 337 InstrItinData<II_C_CC_S , [InstrStage<3, [ALU]>]>, 338 InstrItinData<II_C_CC_D , [InstrStage<3, [ALU]>]>, 339 InstrItinData<II_ADD_D , [InstrStage<4, [ALU]>]>, 340 InstrItinData<II_ADD_S , [InstrStage<4, [ALU]>]>, 341 InstrItinData<II_SUB_D , [InstrStage<4, [ALU]>]>, 342 InstrItinData<II_SUB_S , [InstrStage<4, [ALU]>]>, 343 InstrItinData<II_MUL_S , [InstrStage<7, [ALU]>]>, 344 InstrItinData<II_MADD_S , [InstrStage<7, [ALU]>]>, 345 InstrItinData<II_MSUB_S , [InstrStage<7, [ALU]>]>, 346 InstrItinData<II_NMADD_S , [InstrStage<7, [ALU]>]>, 347 InstrItinData<II_NMSUB_S , [InstrStage<7, [ALU]>]>, 348 InstrItinData<II_MUL_D , [InstrStage<8, [ALU]>]>, 349 InstrItinData<II_MADD_D , [InstrStage<8, [ALU]>]>, 350 InstrItinData<II_MSUB_D , [InstrStage<8, [ALU]>]>, 351 InstrItinData<II_NMADD_D , [InstrStage<8, [ALU]>]>, 352 InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>, 353 InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>, 354 InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>, 355 InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>, 356 InstrItinData<II_SQRT_D , [InstrStage<12, [ALU]>]>, 357 InstrItinData<II_LDC1 , [InstrStage<3, [ALU]>]>, 358 InstrItinData<II_LWC1 , [InstrStage<3, [ALU]>]>, 359 InstrItinData<II_LDXC1 , [InstrStage<3, [ALU]>]>, 360 InstrItinData<II_LWXC1 , [InstrStage<3, [ALU]>]>, 361 InstrItinData<II_LUXC1 , [InstrStage<3, [ALU]>]>, 362 InstrItinData<II_SDC1 , [InstrStage<1, [ALU]>]>, 363 InstrItinData<II_SWC1 , [InstrStage<1, [ALU]>]>, 364 InstrItinData<II_SDXC1 , [InstrStage<1, [ALU]>]>, 365 InstrItinData<II_SWXC1 , [InstrStage<1, [ALU]>]>, 366 InstrItinData<II_SUXC1 , [InstrStage<1, [ALU]>]>, 367 InstrItinData<II_DMFC1 , [InstrStage<2, [ALU]>]>, 368 InstrItinData<II_DMTC1 , [InstrStage<2, [ALU]>]>, 369 InstrItinData<II_MFC1 , [InstrStage<2, [ALU]>]>, 370 InstrItinData<II_MTC1 , [InstrStage<2, [ALU]>]>, 371 InstrItinData<II_MFHC1 , [InstrStage<2, [ALU]>]>, 372 InstrItinData<II_MTHC1 , [InstrStage<2, [ALU]>]> 373 ]>; 374 375 include "MipsScheduleP5600.td" 376
