1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This is the top level entry point for the PowerPC target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // Get the target-independent interfaces which we are implementing. 15 // 16 include "llvm/Target/Target.td" 17 18 //===----------------------------------------------------------------------===// 19 // PowerPC Subtarget features. 20 // 21 22 //===----------------------------------------------------------------------===// 23 // CPU Directives // 24 //===----------------------------------------------------------------------===// 25 26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; 27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; 28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; 29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; 33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; 34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; 35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; 36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; 37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; 38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", 39 "PPC::DIR_E500mc", "">; 40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", 41 "PPC::DIR_E5500", "">; 42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">; 43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">; 44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">; 45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">; 46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; 47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; 48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; 49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">; 50 51 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 52 "Enable 64-bit instructions">; 53 def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 54 "Use software emulation for floating point">; 55 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 56 "Enable 64-bit registers usage for ppc32 [beta]">; 57 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 58 "Use condition-register bits individually">; 59 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 60 "Enable Altivec instructions">; 61 def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 62 "Enable SPE instructions">; 63 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 64 "Enable the MFOCRF instruction">; 65 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 66 "Enable the fsqrt instruction">; 67 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 68 "Enable the fcpsgn instruction">; 69 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 70 "Enable the fre instruction">; 71 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 72 "Enable the fres instruction">; 73 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 74 "Enable the frsqrte instruction">; 75 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 76 "Enable the frsqrtes instruction">; 77 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 78 "Assume higher precision reciprocal estimates">; 79 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 80 "Enable the stfiwx instruction">; 81 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 82 "Enable the lfiwax instruction">; 83 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 84 "Enable the fri[mnpz] instructions">; 85 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 86 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">; 87 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 88 "Enable the isel instruction">; 89 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true", 90 "Enable the popcnt[dw] instructions">; 91 def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 92 "Enable the bpermd instruction">; 93 def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 94 "Enable extended divide instructions">; 95 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 96 "Enable the ldbrx instruction">; 97 def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 98 "Enable the cmpb instruction">; 99 def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 100 "Enable icbt instruction">; 101 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 102 "Enable Book E instructions", 103 [FeatureICBT]>; 104 def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 105 "Has only the msync instruction instead of sync", 106 [FeatureBookE]>; 107 def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 108 "Enable E500/E500mc instructions">; 109 def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 110 "Enable PPC 4xx instructions">; 111 def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 112 "Enable PPC 6xx instructions">; 113 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 114 "Enable QPX instructions">; 115 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 116 "Enable VSX instructions", 117 [FeatureAltivec]>; 118 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 119 "Enable POWER8 Altivec instructions", 120 [FeatureAltivec]>; 121 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 122 "Enable POWER8 Crypto instructions", 123 [FeatureP8Altivec]>; 124 def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 125 "Enable POWER8 vector instructions", 126 [FeatureVSX, FeatureP8Altivec]>; 127 def FeatureDirectMove : 128 SubtargetFeature<"direct-move", "HasDirectMove", "true", 129 "Enable Power8 direct move instructions", 130 [FeatureVSX]>; 131 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 132 "HasPartwordAtomics", "true", 133 "Enable l[bh]arx and st[bh]cx.">; 134 def FeatureInvariantFunctionDescriptors : 135 SubtargetFeature<"invariant-function-descriptors", 136 "HasInvariantFunctionDescriptors", "true", 137 "Assume function descriptors are invariant">; 138 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 139 "Enable Hardware Transactional Memory instructions">; 140 def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 141 "Implement mftb using the mfspr instruction">; 142 def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 143 "Target supports add/load integer fusion.">; 144 def FeatureFloat128 : 145 SubtargetFeature<"float128", "HasFloat128", "true", 146 "Enable the __float128 data type for IEEE-754R Binary128.", 147 [FeatureVSX]>; 148 149 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 150 "Treat vector data stream cache control instructions as deprecated">; 151 152 /* Since new processors generally contain a superset of features of those that 153 came before them, the idea is to make implementations of new processors 154 less error prone and easier to read. 155 Namely: 156 list<SubtargetFeature> Power8FeatureList = ... 157 list<SubtargetFeature> FutureProcessorSpecificFeatureList = 158 [ features that Power8 does not support ] 159 list<SubtargetFeature> FutureProcessorFeatureList = 160 !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList) 161 162 Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as 163 well as providing a single point of definition if the feature set will be 164 used elsewhere. 165 */ 166 def ProcessorFeatures { 167 list<SubtargetFeature> Power7FeatureList = 168 [DirectivePwr7, FeatureAltivec, FeatureVSX, 169 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 170 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 171 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 172 FeatureFPRND, FeatureFPCVT, FeatureISEL, 173 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, 174 Feature64Bit /*, Feature64BitRegs */, 175 FeatureBPERMD, FeatureExtDiv, 176 FeatureMFTB, DeprecatedDST]; 177 list<SubtargetFeature> Power8SpecificFeatures = 178 [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto, 179 FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic, 180 FeatureFusion]; 181 list<SubtargetFeature> Power8FeatureList = 182 !listconcat(Power7FeatureList, Power8SpecificFeatures); 183 } 184 185 // Note: Future features to add when support is extended to more 186 // recent ISA levels: 187 // 188 // DFP p6, p6x, p7 decimal floating-point instructions 189 // POPCNTB p5 through p7 popcntb and related instructions 190 191 //===----------------------------------------------------------------------===// 192 // Classes used for relation maps. 193 //===----------------------------------------------------------------------===// 194 // RecFormRel - Filter class used to relate non-record-form instructions with 195 // their record-form variants. 196 class RecFormRel; 197 198 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 199 // FMA instruction forms with their corresponding factor-killing forms. 200 class AltVSXFMARel { 201 bit IsVSXFMAAlt = 0; 202 } 203 204 //===----------------------------------------------------------------------===// 205 // Relation Map Definitions. 206 //===----------------------------------------------------------------------===// 207 208 def getRecordFormOpcode : InstrMapping { 209 let FilterClass = "RecFormRel"; 210 // Instructions with the same BaseName and Interpretation64Bit values 211 // form a row. 212 let RowFields = ["BaseName", "Interpretation64Bit"]; 213 // Instructions with the same RC value form a column. 214 let ColFields = ["RC"]; 215 // The key column are the non-record-form instructions. 216 let KeyCol = ["0"]; 217 // Value columns RC=1 218 let ValueCols = [["1"]]; 219 } 220 221 def getNonRecordFormOpcode : InstrMapping { 222 let FilterClass = "RecFormRel"; 223 // Instructions with the same BaseName and Interpretation64Bit values 224 // form a row. 225 let RowFields = ["BaseName", "Interpretation64Bit"]; 226 // Instructions with the same RC value form a column. 227 let ColFields = ["RC"]; 228 // The key column are the record-form instructions. 229 let KeyCol = ["1"]; 230 // Value columns are RC=0 231 let ValueCols = [["0"]]; 232 } 233 234 def getAltVSXFMAOpcode : InstrMapping { 235 let FilterClass = "AltVSXFMARel"; 236 // Instructions with the same BaseName and Interpretation64Bit values 237 // form a row. 238 let RowFields = ["BaseName"]; 239 // Instructions with the same RC value form a column. 240 let ColFields = ["IsVSXFMAAlt"]; 241 // The key column are the (default) addend-killing instructions. 242 let KeyCol = ["0"]; 243 // Value columns IsVSXFMAAlt=1 244 let ValueCols = [["1"]]; 245 } 246 247 //===----------------------------------------------------------------------===// 248 // Register File Description 249 //===----------------------------------------------------------------------===// 250 251 include "PPCRegisterInfo.td" 252 include "PPCSchedule.td" 253 include "PPCInstrInfo.td" 254 255 //===----------------------------------------------------------------------===// 256 // PowerPC processors supported. 257 // 258 259 def : Processor<"generic", G3Itineraries, [Directive32, FeatureMFTB]>; 260 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 261 FeatureFRES, FeatureFRSQRTE, 262 FeatureICBT, FeatureBookE, 263 FeatureMSYNC, FeatureMFTB]>; 264 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 265 FeatureFRES, FeatureFRSQRTE, 266 FeatureICBT, FeatureBookE, 267 FeatureMSYNC, FeatureMFTB]>; 268 def : Processor<"601", G3Itineraries, [Directive601]>; 269 def : Processor<"602", G3Itineraries, [Directive602, 270 FeatureMFTB]>; 271 def : Processor<"603", G3Itineraries, [Directive603, 272 FeatureFRES, FeatureFRSQRTE, 273 FeatureMFTB]>; 274 def : Processor<"603e", G3Itineraries, [Directive603, 275 FeatureFRES, FeatureFRSQRTE, 276 FeatureMFTB]>; 277 def : Processor<"603ev", G3Itineraries, [Directive603, 278 FeatureFRES, FeatureFRSQRTE, 279 FeatureMFTB]>; 280 def : Processor<"604", G3Itineraries, [Directive604, 281 FeatureFRES, FeatureFRSQRTE, 282 FeatureMFTB]>; 283 def : Processor<"604e", G3Itineraries, [Directive604, 284 FeatureFRES, FeatureFRSQRTE, 285 FeatureMFTB]>; 286 def : Processor<"620", G3Itineraries, [Directive620, 287 FeatureFRES, FeatureFRSQRTE, 288 FeatureMFTB]>; 289 def : Processor<"750", G4Itineraries, [Directive750, 290 FeatureFRES, FeatureFRSQRTE, 291 FeatureMFTB]>; 292 def : Processor<"g3", G3Itineraries, [Directive750, 293 FeatureFRES, FeatureFRSQRTE, 294 FeatureMFTB]>; 295 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 296 FeatureFRES, FeatureFRSQRTE, 297 FeatureMFTB]>; 298 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 299 FeatureFRES, FeatureFRSQRTE, 300 FeatureMFTB]>; 301 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 302 FeatureFRES, FeatureFRSQRTE, 303 FeatureMFTB]>; 304 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 305 FeatureFRES, FeatureFRSQRTE, 306 FeatureMFTB]>; 307 308 def : ProcessorModel<"970", G5Model, 309 [Directive970, FeatureAltivec, 310 FeatureMFOCRF, FeatureFSqrt, 311 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 312 Feature64Bit /*, Feature64BitRegs */, 313 FeatureMFTB]>; 314 def : ProcessorModel<"g5", G5Model, 315 [Directive970, FeatureAltivec, 316 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 317 FeatureFRES, FeatureFRSQRTE, 318 Feature64Bit /*, Feature64BitRegs */, 319 FeatureMFTB, DeprecatedDST]>; 320 def : ProcessorModel<"e500mc", PPCE500mcModel, 321 [DirectiveE500mc, 322 FeatureSTFIWX, FeatureICBT, FeatureBookE, 323 FeatureISEL, FeatureMFTB]>; 324 def : ProcessorModel<"e5500", PPCE5500Model, 325 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 326 FeatureSTFIWX, FeatureICBT, FeatureBookE, 327 FeatureISEL, FeatureMFTB]>; 328 def : ProcessorModel<"a2", PPCA2Model, 329 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 330 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 331 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 332 FeatureSTFIWX, FeatureLFIWAX, 333 FeatureFPRND, FeatureFPCVT, FeatureISEL, 334 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit 335 /*, Feature64BitRegs */, FeatureMFTB]>; 336 def : ProcessorModel<"a2q", PPCA2Model, 337 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 338 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 339 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 340 FeatureSTFIWX, FeatureLFIWAX, 341 FeatureFPRND, FeatureFPCVT, FeatureISEL, 342 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit 343 /*, Feature64BitRegs */, FeatureQPX, FeatureMFTB]>; 344 def : ProcessorModel<"pwr3", G5Model, 345 [DirectivePwr3, FeatureAltivec, 346 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 347 FeatureSTFIWX, Feature64Bit]>; 348 def : ProcessorModel<"pwr4", G5Model, 349 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 350 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 351 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 352 def : ProcessorModel<"pwr5", G5Model, 353 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 354 FeatureFSqrt, FeatureFRE, FeatureFRES, 355 FeatureFRSQRTE, FeatureFRSQRTES, 356 FeatureSTFIWX, Feature64Bit, 357 FeatureMFTB, DeprecatedDST]>; 358 def : ProcessorModel<"pwr5x", G5Model, 359 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 360 FeatureFSqrt, FeatureFRE, FeatureFRES, 361 FeatureFRSQRTE, FeatureFRSQRTES, 362 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 363 FeatureMFTB, DeprecatedDST]>; 364 def : ProcessorModel<"pwr6", G5Model, 365 [DirectivePwr6, FeatureAltivec, 366 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 367 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 368 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 369 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 370 FeatureMFTB, DeprecatedDST]>; 371 def : ProcessorModel<"pwr6x", G5Model, 372 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 373 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 374 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 375 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 376 FeatureFPRND, Feature64Bit, 377 FeatureMFTB, DeprecatedDST]>; 378 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>; 379 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>; 380 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureMFTB]>; 381 def : ProcessorModel<"ppc64", G5Model, 382 [Directive64, FeatureAltivec, 383 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 384 FeatureFRSQRTE, FeatureSTFIWX, 385 Feature64Bit /*, Feature64BitRegs */, 386 FeatureMFTB]>; 387 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>; 388 389 //===----------------------------------------------------------------------===// 390 // Calling Conventions 391 //===----------------------------------------------------------------------===// 392 393 include "PPCCallingConv.td" 394 395 def PPCInstrInfo : InstrInfo { 396 let isLittleEndianEncoding = 1; 397 398 // FIXME: Unset this when no longer needed! 399 let decodePositionallyEncodedOperands = 1; 400 401 let noNamedPositionallyEncodedOperands = 1; 402 } 403 404 def PPCAsmParser : AsmParser { 405 let ShouldEmitMatchRegisterName = 0; 406 } 407 408 def PPCAsmParserVariant : AsmParserVariant { 409 int Variant = 0; 410 411 // We do not use hard coded registers in asm strings. However, some 412 // InstAlias definitions use immediate literals. Set RegisterPrefix 413 // so that those are not misinterpreted as registers. 414 string RegisterPrefix = "%"; 415 string BreakCharacters = "."; 416 } 417 418 def PPC : Target { 419 // Information about the instructions. 420 let InstructionSet = PPCInstrInfo; 421 422 let AssemblyParsers = [PPCAsmParser]; 423 let AssemblyParserVariants = [PPCAsmParserVariant]; 424 } 425
