1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the PowerPC 64-bit instructions. These patterns are used 11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // 64-bit operands. 17 // 18 def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 let DecoderMethod = "decodeSImmOperand<16>"; 23 } 24 def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29 } 30 def s17imm64 : Operand<i64> { 31 // This operand type is used for addis/lis to allow the assembler parser 32 // to accept immediates in the range -65536..65535 for compatibility with 33 // the GNU assembler. The operand is treated as 16-bit otherwise. 34 let PrintMethod = "printS16ImmOperand"; 35 let EncoderMethod = "getImm16Encoding"; 36 let ParserMatchClass = PPCS17ImmAsmOperand; 37 let DecoderMethod = "decodeSImmOperand<16>"; 38 } 39 def tocentry : Operand<iPTR> { 40 let MIOperandInfo = (ops i64imm:$imm); 41 } 42 def tlsreg : Operand<i64> { 43 let EncoderMethod = "getTLSRegEncoding"; 44 let ParserMatchClass = PPCTLSRegOperand; 45 } 46 def tlsgd : Operand<i64> {} 47 def tlscall : Operand<i64> { 48 let PrintMethod = "printTLSCall"; 49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 50 let EncoderMethod = "getTLSCallEncoding"; 51 } 52 53 //===----------------------------------------------------------------------===// 54 // 64-bit transformation functions. 55 // 56 57 def SHL64 : SDNodeXForm<imm, [{ 58 // Transformation function: 63 - imm 59 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 60 }]>; 61 62 def SRL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 64 - imm 64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 65 : getI32Imm(0, SDLoc(N)); 66 }]>; 67 68 def HI32_48 : SDNodeXForm<imm, [{ 69 // Transformation function: shift the immediate value down into the low bits. 70 return getI32Imm((unsigned short)(N->getZExtValue() >> 32, SDLoc(N))); 71 }]>; 72 73 def HI48_64 : SDNodeXForm<imm, [{ 74 // Transformation function: shift the immediate value down into the low bits. 75 return getI32Imm((unsigned short)(N->getZExtValue() >> 48, SDLoc(N))); 76 }]>; 77 78 79 //===----------------------------------------------------------------------===// 80 // Calls. 81 // 82 83 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 84 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 85 let isReturn = 1, Uses = [LR8, RM] in 86 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 87 [(retflag)]>, Requires<[In64BitMode]>; 88 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 89 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 90 []>, 91 Requires<[In64BitMode]>; 92 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 93 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 94 []>, 95 Requires<[In64BitMode]>; 96 97 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 98 "bcctr 12, $bi, 0", IIC_BrB, []>, 99 Requires<[In64BitMode]>; 100 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 101 "bcctr 4, $bi, 0", IIC_BrB, []>, 102 Requires<[In64BitMode]>; 103 } 104 } 105 106 let Defs = [LR8] in 107 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 108 PPC970_Unit_BRU; 109 110 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 111 let Defs = [CTR8], Uses = [CTR8] in { 112 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 113 "bdz $dst">; 114 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 115 "bdnz $dst">; 116 } 117 118 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 119 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 120 "bdzlr", IIC_BrB, []>; 121 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 122 "bdnzlr", IIC_BrB, []>; 123 } 124 } 125 126 127 128 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 129 // Convenient aliases for call instructions 130 let Uses = [RM] in { 131 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 132 "bl $func", IIC_BrB, []>; // See Pat patterns below. 133 134 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 135 "bl $func", IIC_BrB, []>; 136 137 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 138 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 139 } 140 let Uses = [RM], isCodeGenOnly = 1 in { 141 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 142 (outs), (ins calltarget:$func), 143 "bl $func\n\tnop", IIC_BrB, []>; 144 145 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 146 (outs), (ins tlscall:$func), 147 "bl $func\n\tnop", IIC_BrB, []>; 148 149 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 150 (outs), (ins abscalltarget:$func), 151 "bla $func\n\tnop", IIC_BrB, 152 [(PPCcall_nop (i64 imm:$func))]>; 153 } 154 let Uses = [CTR8, RM] in { 155 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 156 "bctrl", IIC_BrB, [(PPCbctrl)]>, 157 Requires<[In64BitMode]>; 158 159 let isCodeGenOnly = 1 in { 160 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 161 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 162 []>, 163 Requires<[In64BitMode]>; 164 165 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 166 "bcctrl 12, $bi, 0", IIC_BrB, []>, 167 Requires<[In64BitMode]>; 168 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 169 "bcctrl 4, $bi, 0", IIC_BrB, []>, 170 Requires<[In64BitMode]>; 171 } 172 } 173 } 174 175 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 176 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 177 def BCTRL8_LDinto_toc : 178 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 179 (ins memrix:$src), 180 "bctrl\n\tld 2, $src", IIC_BrB, 181 [(PPCbctrl_load_toc ixaddr:$src)]>, 182 Requires<[In64BitMode]>; 183 } 184 185 } // Interpretation64Bit 186 187 // FIXME: Duplicating this for the asm parser should be unnecessary, but the 188 // previous definition must be marked as CodeGen only to prevent decoding 189 // conflicts. 190 let Interpretation64Bit = 1, isAsmParserOnly = 1 in 191 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 192 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 193 "bl $func", IIC_BrB, []>; 194 195 // Calls 196 def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 197 (BL8 tglobaladdr:$dst)>; 198 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 199 (BL8_NOP tglobaladdr:$dst)>; 200 201 def : Pat<(PPCcall (i64 texternalsym:$dst)), 202 (BL8 texternalsym:$dst)>; 203 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 204 (BL8_NOP texternalsym:$dst)>; 205 206 // Atomic operations 207 let usesCustomInserter = 1 in { 208 let Defs = [CR0] in { 209 def ATOMIC_LOAD_ADD_I64 : Pseudo< 210 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 211 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 212 def ATOMIC_LOAD_SUB_I64 : Pseudo< 213 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 214 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 215 def ATOMIC_LOAD_OR_I64 : Pseudo< 216 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 217 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 218 def ATOMIC_LOAD_XOR_I64 : Pseudo< 219 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 220 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 221 def ATOMIC_LOAD_AND_I64 : Pseudo< 222 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 223 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 224 def ATOMIC_LOAD_NAND_I64 : Pseudo< 225 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 226 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 227 228 def ATOMIC_CMP_SWAP_I64 : Pseudo< 229 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 230 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 231 232 def ATOMIC_SWAP_I64 : Pseudo< 233 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 234 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 235 } 236 } 237 238 // Instructions to support atomic operations 239 let mayLoad = 1, hasSideEffects = 0 in { 240 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 241 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 242 243 // Instruction to support lock versions of atomics 244 // (EH=1 - see Power ISA 2.07 Book II 4.4.2) 245 def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 246 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 247 } 248 249 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in 250 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 251 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT; 252 253 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 254 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 255 def TCRETURNdi8 :Pseudo< (outs), 256 (ins calltarget:$dst, i32imm:$offset), 257 "#TC_RETURNd8 $dst $offset", 258 []>; 259 260 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 261 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 262 "#TC_RETURNa8 $func $offset", 263 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 264 265 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 266 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 267 "#TC_RETURNr8 $dst $offset", 268 []>; 269 270 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 271 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 272 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 273 []>, 274 Requires<[In64BitMode]>; 275 276 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 277 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 278 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 279 "b $dst", IIC_BrB, 280 []>; 281 282 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 283 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 284 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 285 "ba $dst", IIC_BrB, 286 []>; 287 } // Interpretation64Bit 288 289 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 290 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 291 292 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 293 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 294 295 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 296 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 297 298 299 // 64-bit CR instructions 300 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 301 let hasSideEffects = 0 in { 302 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 303 "mtocrf $FXM, $ST", IIC_BrMCRX>, 304 PPC970_DGroup_First, PPC970_Unit_CRU; 305 306 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 307 "mtcrf $FXM, $rS", IIC_BrMCRX>, 308 PPC970_MicroCode, PPC970_Unit_CRU; 309 310 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. 311 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 312 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 313 PPC970_DGroup_First, PPC970_Unit_CRU; 314 315 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 316 "mfcr $rT", IIC_SprMFCR>, 317 PPC970_MicroCode, PPC970_Unit_CRU; 318 } // hasSideEffects = 0 319 320 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 321 let Defs = [CTR8] in 322 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 323 "#EH_SJLJ_SETJMP64", 324 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 325 Requires<[In64BitMode]>; 326 let isTerminator = 1 in 327 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 328 "#EH_SJLJ_LONGJMP64", 329 [(PPCeh_sjlj_longjmp addr:$buf)]>, 330 Requires<[In64BitMode]>; 331 } 332 333 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 334 "mfspr $RT, $SPR", IIC_SprMFSPR>; 335 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 336 "mtspr $SPR, $RT", IIC_SprMTSPR>; 337 338 339 //===----------------------------------------------------------------------===// 340 // 64-bit SPR manipulation instrs. 341 342 let Uses = [CTR8] in { 343 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 344 "mfctr $rT", IIC_SprMFSPR>, 345 PPC970_DGroup_First, PPC970_Unit_FXU; 346 } 347 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 348 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 349 "mtctr $rS", IIC_SprMTSPR>, 350 PPC970_DGroup_First, PPC970_Unit_FXU; 351 } 352 let hasSideEffects = 1, Defs = [CTR8] in { 353 let Pattern = [(int_ppc_mtctr i64:$rS)] in 354 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 355 "mtctr $rS", IIC_SprMTSPR>, 356 PPC970_DGroup_First, PPC970_Unit_FXU; 357 } 358 359 let Pattern = [(set i64:$rT, readcyclecounter)] in 360 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 361 "mfspr $rT, 268", IIC_SprMFTB>, 362 PPC970_DGroup_First, PPC970_Unit_FXU; 363 // Note that encoding mftb using mfspr is now the preferred form, 364 // and has been since at least ISA v2.03. The mftb instruction has 365 // now been phased out. Using mfspr, however, is known not to work on 366 // the POWER3. 367 368 let Defs = [X1], Uses = [X1] in 369 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 370 [(set i64:$result, 371 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 372 def DYNAREAOFFSET8 : Pseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 373 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 374 375 let Defs = [LR8] in { 376 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 377 "mtlr $rS", IIC_SprMTSPR>, 378 PPC970_DGroup_First, PPC970_Unit_FXU; 379 } 380 let Uses = [LR8] in { 381 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 382 "mflr $rT", IIC_SprMFSPR>, 383 PPC970_DGroup_First, PPC970_Unit_FXU; 384 } 385 } // Interpretation64Bit 386 387 //===----------------------------------------------------------------------===// 388 // Fixed point instructions. 389 // 390 391 let PPC970_Unit = 1 in { // FXU Operations. 392 let Interpretation64Bit = 1 in { 393 let hasSideEffects = 0 in { 394 let isCodeGenOnly = 1 in { 395 396 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 397 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 398 "li $rD, $imm", IIC_IntSimple, 399 [(set i64:$rD, imm64SExt16:$imm)]>; 400 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 401 "lis $rD, $imm", IIC_IntSimple, 402 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 403 } 404 405 // Logical ops. 406 let isCommutable = 1 in { 407 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 408 "nand", "$rA, $rS, $rB", IIC_IntSimple, 409 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 410 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 411 "and", "$rA, $rS, $rB", IIC_IntSimple, 412 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 413 } // isCommutable 414 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 415 "andc", "$rA, $rS, $rB", IIC_IntSimple, 416 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 417 let isCommutable = 1 in { 418 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 419 "or", "$rA, $rS, $rB", IIC_IntSimple, 420 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 421 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 422 "nor", "$rA, $rS, $rB", IIC_IntSimple, 423 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 424 } // isCommutable 425 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 426 "orc", "$rA, $rS, $rB", IIC_IntSimple, 427 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 428 let isCommutable = 1 in { 429 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 430 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 431 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 432 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 433 "xor", "$rA, $rS, $rB", IIC_IntSimple, 434 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 435 } // let isCommutable = 1 436 437 // Logical ops with immediate. 438 let Defs = [CR0] in { 439 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 440 "andi. $dst, $src1, $src2", IIC_IntGeneral, 441 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 442 isDOT; 443 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 444 "andis. $dst, $src1, $src2", IIC_IntGeneral, 445 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 446 isDOT; 447 } 448 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 449 "ori $dst, $src1, $src2", IIC_IntSimple, 450 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 451 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 452 "oris $dst, $src1, $src2", IIC_IntSimple, 453 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 454 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 455 "xori $dst, $src1, $src2", IIC_IntSimple, 456 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 457 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 458 "xoris $dst, $src1, $src2", IIC_IntSimple, 459 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 460 461 let isCommutable = 1 in 462 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 463 "add", "$rT, $rA, $rB", IIC_IntSimple, 464 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 465 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 466 // initial-exec thread-local storage model. 467 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 468 "add $rT, $rA, $rB", IIC_IntSimple, 469 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 470 471 let isCommutable = 1 in 472 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 473 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 474 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 475 PPC970_DGroup_Cracked; 476 477 let Defs = [CARRY] in 478 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 479 "addic $rD, $rA, $imm", IIC_IntGeneral, 480 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 481 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 482 "addi $rD, $rA, $imm", IIC_IntSimple, 483 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 484 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 485 "addis $rD, $rA, $imm", IIC_IntSimple, 486 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 487 488 let Defs = [CARRY] in { 489 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 490 "subfic $rD, $rA, $imm", IIC_IntGeneral, 491 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 492 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 493 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 494 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 495 PPC970_DGroup_Cracked; 496 } 497 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 498 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 499 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 500 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 501 "neg", "$rT, $rA", IIC_IntSimple, 502 [(set i64:$rT, (ineg i64:$rA))]>; 503 let Uses = [CARRY] in { 504 let isCommutable = 1 in 505 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 506 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 507 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 508 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 509 "addme", "$rT, $rA", IIC_IntGeneral, 510 [(set i64:$rT, (adde i64:$rA, -1))]>; 511 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 512 "addze", "$rT, $rA", IIC_IntGeneral, 513 [(set i64:$rT, (adde i64:$rA, 0))]>; 514 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 515 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 516 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 517 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 518 "subfme", "$rT, $rA", IIC_IntGeneral, 519 [(set i64:$rT, (sube -1, i64:$rA))]>; 520 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 521 "subfze", "$rT, $rA", IIC_IntGeneral, 522 [(set i64:$rT, (sube 0, i64:$rA))]>; 523 } 524 } // isCodeGenOnly 525 526 // FIXME: Duplicating this for the asm parser should be unnecessary, but the 527 // previous definition must be marked as CodeGen only to prevent decoding 528 // conflicts. 529 let isAsmParserOnly = 1 in 530 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 531 "add $rT, $rA, $rB", IIC_IntSimple, []>; 532 533 let isCommutable = 1 in { 534 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 535 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 536 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 537 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 538 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 539 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 540 } // isCommutable 541 } 542 } // Interpretation64Bit 543 544 let isCompare = 1, hasSideEffects = 0 in { 545 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 546 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 547 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 548 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 549 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 550 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 551 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 552 "cmpldi $dst, $src1, $src2", 553 IIC_IntCompare>, isPPC64; 554 } 555 556 let hasSideEffects = 0 in { 557 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 558 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 559 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 560 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 561 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 562 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 563 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 564 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 565 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 566 567 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 568 defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 569 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 570 571 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 572 "extsb", "$rA, $rS", IIC_IntSimple, 573 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 574 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 575 "extsh", "$rA, $rS", IIC_IntSimple, 576 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 577 578 defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 579 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 580 defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 581 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 582 } // Interpretation64Bit 583 584 // For fast-isel: 585 let isCodeGenOnly = 1 in { 586 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 587 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 588 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 589 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 590 } // isCodeGenOnly for fast-isel 591 592 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 593 "extsw", "$rA, $rS", IIC_IntSimple, 594 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 595 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 596 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 597 "extsw", "$rA, $rS", IIC_IntSimple, 598 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 599 600 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 601 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 602 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 603 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 604 "cntlzd", "$rA, $rS", IIC_IntGeneral, 605 [(set i64:$rA, (ctlz i64:$rS))]>; 606 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 607 "popcntd $rA, $rS", IIC_IntGeneral, 608 [(set i64:$rA, (ctpop i64:$rS))]>; 609 def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 610 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 611 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 612 isPPC64, Requires<[HasBPERMD]>; 613 614 let isCodeGenOnly = 1, isCommutable = 1 in 615 def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 616 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 617 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 618 619 // popcntw also does a population count on the high 32 bits (storing the 620 // results in the high 32-bits of the output). We'll ignore that here (which is 621 // safe because we never separately use the high part of the 64-bit registers). 622 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 623 "popcntw $rA, $rS", IIC_IntGeneral, 624 [(set i32:$rA, (ctpop i32:$rS))]>; 625 626 defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 627 "divd", "$rT, $rA, $rB", IIC_IntDivD, 628 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 629 defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 630 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 631 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 632 def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 633 "divde $rT, $rA, $rB", IIC_IntDivD, 634 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 635 isPPC64, Requires<[HasExtDiv]>; 636 let Defs = [CR0] in 637 def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 638 "divde. $rT, $rA, $rB", IIC_IntDivD, 639 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 640 isPPC64, Requires<[HasExtDiv]>; 641 def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 642 "divdeu $rT, $rA, $rB", IIC_IntDivD, 643 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 644 isPPC64, Requires<[HasExtDiv]>; 645 let Defs = [CR0] in 646 def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 647 "divdeu. $rT, $rA, $rB", IIC_IntDivD, 648 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 649 isPPC64, Requires<[HasExtDiv]>; 650 let isCommutable = 1 in 651 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 652 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 653 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 654 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 655 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 656 "mulli $rD, $rA, $imm", IIC_IntMulLI, 657 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 658 } 659 660 let hasSideEffects = 0 in { 661 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 662 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 663 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 664 []>, isPPC64, RegConstraint<"$rSi = $rA">, 665 NoEncode<"$rSi">; 666 667 // Rotate instructions. 668 defm RLDCL : MDSForm_1r<30, 8, 669 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 670 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 671 []>, isPPC64; 672 defm RLDCR : MDSForm_1r<30, 9, 673 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 674 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 675 []>, isPPC64; 676 defm RLDICL : MDForm_1r<30, 0, 677 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 678 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 679 []>, isPPC64; 680 // For fast-isel: 681 let isCodeGenOnly = 1 in 682 def RLDICL_32_64 : MDForm_1<30, 0, 683 (outs g8rc:$rA), 684 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 685 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 686 []>, isPPC64; 687 // End fast-isel. 688 defm RLDICR : MDForm_1r<30, 1, 689 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 690 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 691 []>, isPPC64; 692 defm RLDIC : MDForm_1r<30, 2, 693 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 694 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 695 []>, isPPC64; 696 697 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 698 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 699 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 700 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 701 []>; 702 703 defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 704 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 705 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 706 []>; 707 708 // RLWIMI can be commuted if the rotate amount is zero. 709 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 710 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 711 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 712 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 713 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 714 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 715 716 let isSelect = 1 in 717 def ISEL8 : AForm_4<31, 15, 718 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 719 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 720 []>; 721 } // Interpretation64Bit 722 } // hasSideEffects = 0 723 } // End FXU Operations. 724 725 726 //===----------------------------------------------------------------------===// 727 // Load/Store instructions. 728 // 729 730 731 // Sign extending loads. 732 let PPC970_Unit = 2 in { 733 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 734 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 735 "lha $rD, $src", IIC_LdStLHA, 736 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 737 PPC970_DGroup_Cracked; 738 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 739 "lwa $rD, $src", IIC_LdStLWA, 740 [(set i64:$rD, 741 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 742 PPC970_DGroup_Cracked; 743 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 744 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 745 "lhax $rD, $src", IIC_LdStLHA, 746 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 747 PPC970_DGroup_Cracked; 748 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 749 "lwax $rD, $src", IIC_LdStLHA, 750 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 751 PPC970_DGroup_Cracked; 752 // For fast-isel: 753 let isCodeGenOnly = 1, mayLoad = 1 in { 754 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 755 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 756 PPC970_DGroup_Cracked; 757 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), 758 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 759 PPC970_DGroup_Cracked; 760 } // end fast-isel isCodeGenOnly 761 762 // Update forms. 763 let mayLoad = 1, hasSideEffects = 0 in { 764 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 765 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 766 (ins memri:$addr), 767 "lhau $rD, $addr", IIC_LdStLHAU, 768 []>, RegConstraint<"$addr.reg = $ea_result">, 769 NoEncode<"$ea_result">; 770 // NO LWAU! 771 772 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 773 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 774 (ins memrr:$addr), 775 "lhaux $rD, $addr", IIC_LdStLHAUX, 776 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 777 NoEncode<"$ea_result">; 778 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 779 (ins memrr:$addr), 780 "lwaux $rD, $addr", IIC_LdStLHAUX, 781 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 782 NoEncode<"$ea_result">, isPPC64; 783 } 784 } 785 786 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 787 // Zero extending loads. 788 let PPC970_Unit = 2 in { 789 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 790 "lbz $rD, $src", IIC_LdStLoad, 791 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 792 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 793 "lhz $rD, $src", IIC_LdStLoad, 794 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 795 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 796 "lwz $rD, $src", IIC_LdStLoad, 797 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 798 799 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 800 "lbzx $rD, $src", IIC_LdStLoad, 801 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 802 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 803 "lhzx $rD, $src", IIC_LdStLoad, 804 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 805 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 806 "lwzx $rD, $src", IIC_LdStLoad, 807 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 808 809 810 // Update forms. 811 let mayLoad = 1, hasSideEffects = 0 in { 812 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 813 "lbzu $rD, $addr", IIC_LdStLoadUpd, 814 []>, RegConstraint<"$addr.reg = $ea_result">, 815 NoEncode<"$ea_result">; 816 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 817 "lhzu $rD, $addr", IIC_LdStLoadUpd, 818 []>, RegConstraint<"$addr.reg = $ea_result">, 819 NoEncode<"$ea_result">; 820 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 821 "lwzu $rD, $addr", IIC_LdStLoadUpd, 822 []>, RegConstraint<"$addr.reg = $ea_result">, 823 NoEncode<"$ea_result">; 824 825 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 826 (ins memrr:$addr), 827 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 828 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 829 NoEncode<"$ea_result">; 830 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 831 (ins memrr:$addr), 832 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 833 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 834 NoEncode<"$ea_result">; 835 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 836 (ins memrr:$addr), 837 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 838 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 839 NoEncode<"$ea_result">; 840 } 841 } 842 } // Interpretation64Bit 843 844 845 // Full 8-byte loads. 846 let PPC970_Unit = 2 in { 847 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 848 "ld $rD, $src", IIC_LdStLD, 849 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 850 // The following four definitions are selected for small code model only. 851 // Otherwise, we need to create two instructions to form a 32-bit offset, 852 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 853 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 854 "#LDtoc", 855 [(set i64:$rD, 856 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 857 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 858 "#LDtocJTI", 859 [(set i64:$rD, 860 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 861 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 862 "#LDtocCPT", 863 [(set i64:$rD, 864 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 865 def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 866 "#LDtocCPT", 867 [(set i64:$rD, 868 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 869 870 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 871 "ldx $rD, $src", IIC_LdStLD, 872 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 873 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 874 "ldbrx $rD, $src", IIC_LdStLoad, 875 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 876 877 let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 878 def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src), 879 "lhbrx $rD, $src", IIC_LdStLoad, []>; 880 def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src), 881 "lwbrx $rD, $src", IIC_LdStLoad, []>; 882 } 883 884 let mayLoad = 1, hasSideEffects = 0 in { 885 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 886 "ldu $rD, $addr", IIC_LdStLDU, 887 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 888 NoEncode<"$ea_result">; 889 890 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 891 (ins memrr:$addr), 892 "ldux $rD, $addr", IIC_LdStLDUX, 893 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 894 NoEncode<"$ea_result">, isPPC64; 895 } 896 } 897 898 // Support for medium and large code model. 899 let hasSideEffects = 0 in { 900 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 901 "#ADDIStocHA", []>, isPPC64; 902 let mayLoad = 1 in 903 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 904 "#LDtocL", []>, isPPC64; 905 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 906 "#ADDItocL", []>, isPPC64; 907 } 908 909 // Support for thread-local storage. 910 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 911 "#ADDISgotTprelHA", 912 [(set i64:$rD, 913 (PPCaddisGotTprelHA i64:$reg, 914 tglobaltlsaddr:$disp))]>, 915 isPPC64; 916 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 917 "#LDgotTprelL", 918 [(set i64:$rD, 919 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 920 isPPC64; 921 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 922 (ADD8TLS $in, tglobaltlsaddr:$g)>; 923 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 924 "#ADDIStlsgdHA", 925 [(set i64:$rD, 926 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 927 isPPC64; 928 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 929 "#ADDItlsgdL", 930 [(set i64:$rD, 931 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 932 isPPC64; 933 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is 934 // explicitly defined when this op is created, so not mentioned here. 935 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 936 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 937 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 938 "#GETtlsADDR", 939 [(set i64:$rD, 940 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 941 isPPC64; 942 // Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 943 // are true defines while the rest of the Defs are clobbers. 944 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 945 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 946 in 947 def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD), 948 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 949 "#ADDItlsgdLADDR", 950 [(set i64:$rD, 951 (PPCaddiTlsgdLAddr i64:$reg, 952 tglobaltlsaddr:$disp, 953 tglobaltlsaddr:$sym))]>, 954 isPPC64; 955 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 956 "#ADDIStlsldHA", 957 [(set i64:$rD, 958 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 959 isPPC64; 960 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 961 "#ADDItlsldL", 962 [(set i64:$rD, 963 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 964 isPPC64; 965 // LR8 is a true define, while the rest of the Defs are clobbers. X3 is 966 // explicitly defined when this op is created, so not mentioned here. 967 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 968 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 969 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 970 "#GETtlsldADDR", 971 [(set i64:$rD, 972 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 973 isPPC64; 974 // Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 975 // are true defines, while the rest of the Defs are clobbers. 976 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 977 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 978 in 979 def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD), 980 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 981 "#ADDItlsldLADDR", 982 [(set i64:$rD, 983 (PPCaddiTlsldLAddr i64:$reg, 984 tglobaltlsaddr:$disp, 985 tglobaltlsaddr:$sym))]>, 986 isPPC64; 987 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 988 "#ADDISdtprelHA", 989 [(set i64:$rD, 990 (PPCaddisDtprelHA i64:$reg, 991 tglobaltlsaddr:$disp))]>, 992 isPPC64; 993 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 994 "#ADDIdtprelL", 995 [(set i64:$rD, 996 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 997 isPPC64; 998 999 let PPC970_Unit = 2 in { 1000 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1001 // Truncating stores. 1002 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1003 "stb $rS, $src", IIC_LdStStore, 1004 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1005 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1006 "sth $rS, $src", IIC_LdStStore, 1007 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1008 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1009 "stw $rS, $src", IIC_LdStStore, 1010 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1011 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1012 "stbx $rS, $dst", IIC_LdStStore, 1013 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1014 PPC970_DGroup_Cracked; 1015 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1016 "sthx $rS, $dst", IIC_LdStStore, 1017 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1018 PPC970_DGroup_Cracked; 1019 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1020 "stwx $rS, $dst", IIC_LdStStore, 1021 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1022 PPC970_DGroup_Cracked; 1023 } // Interpretation64Bit 1024 1025 // Normal 8-byte stores. 1026 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1027 "std $rS, $dst", IIC_LdStSTD, 1028 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 1029 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1030 "stdx $rS, $dst", IIC_LdStSTD, 1031 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 1032 PPC970_DGroup_Cracked; 1033 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1034 "stdbrx $rS, $dst", IIC_LdStStore, 1035 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1036 PPC970_DGroup_Cracked; 1037 } 1038 1039 // Stores with Update (pre-inc). 1040 let PPC970_Unit = 2, mayStore = 1 in { 1041 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1042 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1043 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1044 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1045 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1046 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1047 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1048 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1049 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1050 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1051 1052 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1053 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1054 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1055 PPC970_DGroup_Cracked; 1056 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1057 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1058 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1059 PPC970_DGroup_Cracked; 1060 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1061 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1062 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1063 PPC970_DGroup_Cracked; 1064 } // Interpretation64Bit 1065 1066 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 1067 "stdu $rS, $dst", IIC_LdStSTDU, []>, 1068 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1069 isPPC64; 1070 1071 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1072 "stdux $rS, $dst", IIC_LdStSTDUX, []>, 1073 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1074 PPC970_DGroup_Cracked, isPPC64; 1075 } 1076 1077 // Patterns to match the pre-inc stores. We can't put the patterns on 1078 // the instruction definitions directly as ISel wants the address base 1079 // and offset to be separate operands, not a single complex operand. 1080 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1081 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1082 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1083 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1084 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1085 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1086 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1087 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1088 1089 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1090 (STBUX8 $rS, $ptrreg, $ptroff)>; 1091 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1092 (STHUX8 $rS, $ptrreg, $ptroff)>; 1093 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1094 (STWUX8 $rS, $ptrreg, $ptroff)>; 1095 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1096 (STDUX $rS, $ptrreg, $ptroff)>; 1097 1098 1099 //===----------------------------------------------------------------------===// 1100 // Floating point instructions. 1101 // 1102 1103 1104 let PPC970_Unit = 3, hasSideEffects = 0, 1105 Uses = [RM] in { // FPU Operations. 1106 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1107 "fcfid", "$frD, $frB", IIC_FPGeneral, 1108 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1109 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1110 "fctid", "$frD, $frB", IIC_FPGeneral, 1111 []>, isPPC64; 1112 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1113 "fctidz", "$frD, $frB", IIC_FPGeneral, 1114 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1115 1116 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1117 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1118 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1119 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1120 "fcfids", "$frD, $frB", IIC_FPGeneral, 1121 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1122 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1123 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1124 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1125 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1126 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1127 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1128 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1129 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1130 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1131 } 1132 1133 1134 //===----------------------------------------------------------------------===// 1135 // Instruction Patterns 1136 // 1137 1138 // Extensions and truncates to/from 32-bit regs. 1139 def : Pat<(i64 (zext i32:$in)), 1140 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1141 0, 32)>; 1142 def : Pat<(i64 (anyext i32:$in)), 1143 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1144 def : Pat<(i32 (trunc i64:$in)), 1145 (EXTRACT_SUBREG $in, sub_32)>; 1146 1147 // Implement the 'not' operation with the NOR instruction. 1148 // (we could use the default xori pattern, but nor has lower latency on some 1149 // cores (such as the A2)). 1150 def i64not : OutPatFrag<(ops node:$in), 1151 (NOR8 $in, $in)>; 1152 def : Pat<(not i64:$in), 1153 (i64not $in)>; 1154 1155 // Extending loads with i64 targets. 1156 def : Pat<(zextloadi1 iaddr:$src), 1157 (LBZ8 iaddr:$src)>; 1158 def : Pat<(zextloadi1 xaddr:$src), 1159 (LBZX8 xaddr:$src)>; 1160 def : Pat<(extloadi1 iaddr:$src), 1161 (LBZ8 iaddr:$src)>; 1162 def : Pat<(extloadi1 xaddr:$src), 1163 (LBZX8 xaddr:$src)>; 1164 def : Pat<(extloadi8 iaddr:$src), 1165 (LBZ8 iaddr:$src)>; 1166 def : Pat<(extloadi8 xaddr:$src), 1167 (LBZX8 xaddr:$src)>; 1168 def : Pat<(extloadi16 iaddr:$src), 1169 (LHZ8 iaddr:$src)>; 1170 def : Pat<(extloadi16 xaddr:$src), 1171 (LHZX8 xaddr:$src)>; 1172 def : Pat<(extloadi32 iaddr:$src), 1173 (LWZ8 iaddr:$src)>; 1174 def : Pat<(extloadi32 xaddr:$src), 1175 (LWZX8 xaddr:$src)>; 1176 1177 // Standard shifts. These are represented separately from the real shifts above 1178 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1179 // amounts. 1180 def : Pat<(sra i64:$rS, i32:$rB), 1181 (SRAD $rS, $rB)>; 1182 def : Pat<(srl i64:$rS, i32:$rB), 1183 (SRD $rS, $rB)>; 1184 def : Pat<(shl i64:$rS, i32:$rB), 1185 (SLD $rS, $rB)>; 1186 1187 // SHL/SRL 1188 def : Pat<(shl i64:$in, (i32 imm:$imm)), 1189 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1190 def : Pat<(srl i64:$in, (i32 imm:$imm)), 1191 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1192 1193 // ROTL 1194 def : Pat<(rotl i64:$in, i32:$sh), 1195 (RLDCL $in, $sh, 0)>; 1196 def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1197 (RLDICL $in, imm:$imm, 0)>; 1198 1199 // Hi and Lo for Darwin Global Addresses. 1200 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1201 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1202 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1203 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1204 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1205 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1206 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1207 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1208 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1209 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1210 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1211 (ADDI8 $in, tglobaltlsaddr:$g)>; 1212 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1213 (ADDIS8 $in, tglobaladdr:$g)>; 1214 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1215 (ADDIS8 $in, tconstpool:$g)>; 1216 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1217 (ADDIS8 $in, tjumptable:$g)>; 1218 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1219 (ADDIS8 $in, tblockaddress:$g)>; 1220 1221 // Patterns to match r+r indexed loads and stores for 1222 // addresses without at least 4-byte alignment. 1223 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1224 (LWAX xoaddr:$src)>; 1225 def : Pat<(i64 (unaligned4load xoaddr:$src)), 1226 (LDX xoaddr:$src)>; 1227 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1228 (STDX $rS, xoaddr:$dst)>; 1229 1230 // 64-bits atomic loads and stores 1231 def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>; 1232 def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>; 1233 1234 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1235 def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1236
