1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the subset of the 32-bit PowerPC instruction set, as used 11 // by the PowerPC instruction selector. 12 // 13 //===----------------------------------------------------------------------===// 14 15 include "PPCInstrFormats.td" 16 17 //===----------------------------------------------------------------------===// 18 // PowerPC specific type constraints. 19 // 20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22 ]>; 23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 24 SDTCisVT<0, f64>, SDTCisPtrTy<1> 25 ]>; 26 27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 29 SDTCisVT<1, i32> ]>; 30 def SDT_PPCvperm : SDTypeProfile<1, 3, [ 31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 32 ]>; 33 34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 36 ]>; 37 38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 40 ]>; 41 42 def SDT_PPClbrx : SDTypeProfile<1, 2, [ 43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 44 ]>; 45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 47 ]>; 48 49 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 50 SDTCisPtrTy<0>, SDTCisVT<1, i32> 51 ]>; 52 53 def tocentry32 : Operand<iPTR> { 54 let MIOperandInfo = (ops i32imm:$imm); 55 } 56 57 def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 58 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 59 ]>; 60 def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 61 SDTCisVec<0>, SDTCisInt<1> 62 ]>; 63 def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 64 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 65 ]>; 66 def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 67 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 68 ]>; 69 70 def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 71 SDTCisVec<0>, SDTCisVec<1> 72 ]>; 73 74 def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 75 SDTCisVec<0>, SDTCisPtrTy<1> 76 ]>; 77 78 //===----------------------------------------------------------------------===// 79 // PowerPC specific DAG Nodes. 80 // 81 82 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 83 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 84 85 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 86 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 87 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 88 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 89 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 90 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 91 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 92 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 93 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 94 [SDNPHasChain, SDNPMayStore]>; 95 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 96 [SDNPHasChain, SDNPMayLoad]>; 97 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 98 [SDNPHasChain, SDNPMayLoad]>; 99 100 // Extract FPSCR (not modeled at the DAG level). 101 def PPCmffs : SDNode<"PPCISD::MFFS", 102 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>; 103 104 // Perform FADD in round-to-zero mode. 105 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 106 107 108 def PPCfsel : SDNode<"PPCISD::FSEL", 109 // Type constraint for fsel. 110 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 111 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 112 113 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 114 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 115 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 116 [SDNPMayLoad, SDNPMemOperand]>; 117 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 118 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 119 120 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 121 122 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 123 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 124 [SDNPMayLoad]>; 125 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 126 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 127 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 128 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 129 def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 130 SDTypeProfile<1, 3, [ 131 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 132 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 133 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 134 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 135 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 136 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 137 SDTypeProfile<1, 3, [ 138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 139 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 140 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 141 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 142 143 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 144 145 def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>; 146 def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>; 147 def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>; 148 def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>; 149 150 def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>; 151 152 def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb, 153 [SDNPHasChain, SDNPMayLoad]>; 154 155 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 156 157 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 158 // amounts. These nodes are generated by the multi-precision shift code. 159 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 160 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 161 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 162 163 // These are target-independent nodes, but have target-specific formats. 164 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 165 [SDNPHasChain, SDNPOutGlue]>; 166 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 167 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 168 169 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 170 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 171 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 172 SDNPVariadic]>; 173 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 175 SDNPVariadic]>; 176 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 177 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 178 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 179 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 180 SDNPVariadic]>; 181 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 182 SDTypeProfile<0, 1, []>, 183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 184 SDNPVariadic]>; 185 186 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 187 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 188 189 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 190 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 191 192 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 193 SDTypeProfile<1, 1, [SDTCisInt<0>, 194 SDTCisPtrTy<1>]>, 195 [SDNPHasChain, SDNPSideEffect]>; 196 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 197 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 198 [SDNPHasChain, SDNPSideEffect]>; 199 200 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 201 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 202 [SDNPHasChain, SDNPSideEffect]>; 203 204 def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 205 [SDNPHasChain, SDNPSideEffect]>; 206 def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 207 def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 208 [SDNPHasChain, SDNPSideEffect]>; 209 210 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 211 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 212 213 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 214 [SDNPHasChain, SDNPOptInGlue]>; 215 216 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 217 [SDNPHasChain, SDNPMayLoad]>; 218 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 219 [SDNPHasChain, SDNPMayStore]>; 220 221 // Instructions to set/unset CR bit 6 for SVR4 vararg calls 222 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 223 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 224 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 225 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 226 227 // Instructions to support dynamic alloca. 228 def SDTDynOp : SDTypeProfile<1, 2, []>; 229 def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 230 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 231 def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 232 233 //===----------------------------------------------------------------------===// 234 // PowerPC specific transformation functions and pattern fragments. 235 // 236 237 def SHL32 : SDNodeXForm<imm, [{ 238 // Transformation function: 31 - imm 239 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 240 }]>; 241 242 def SRL32 : SDNodeXForm<imm, [{ 243 // Transformation function: 32 - imm 244 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 245 : getI32Imm(0, SDLoc(N)); 246 }]>; 247 248 def LO16 : SDNodeXForm<imm, [{ 249 // Transformation function: get the low 16 bits. 250 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 251 }]>; 252 253 def HI16 : SDNodeXForm<imm, [{ 254 // Transformation function: shift the immediate value down into the low bits. 255 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 256 }]>; 257 258 def HA16 : SDNodeXForm<imm, [{ 259 // Transformation function: shift the immediate value down into the low bits. 260 signed int Val = N->getZExtValue(); 261 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 262 }]>; 263 def MB : SDNodeXForm<imm, [{ 264 // Transformation function: get the start bit of a mask 265 unsigned mb = 0, me; 266 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 267 return getI32Imm(mb, SDLoc(N)); 268 }]>; 269 270 def ME : SDNodeXForm<imm, [{ 271 // Transformation function: get the end bit of a mask 272 unsigned mb, me = 0; 273 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 274 return getI32Imm(me, SDLoc(N)); 275 }]>; 276 def maskimm32 : PatLeaf<(imm), [{ 277 // maskImm predicate - True if immediate is a run of ones. 278 unsigned mb, me; 279 if (N->getValueType(0) == MVT::i32) 280 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 281 else 282 return false; 283 }]>; 284 285 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 286 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 287 // sign extended field. Used by instructions like 'addi'. 288 return (int32_t)Imm == (short)Imm; 289 }]>; 290 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 291 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 292 // sign extended field. Used by instructions like 'addi'. 293 return (int64_t)Imm == (short)Imm; 294 }]>; 295 def immZExt16 : PatLeaf<(imm), [{ 296 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 297 // field. Used by instructions like 'ori'. 298 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 299 }], LO16>; 300 301 // imm16Shifted* - These match immediates where the low 16-bits are zero. There 302 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 303 // identical in 32-bit mode, but in 64-bit mode, they return true if the 304 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits 305 // clear). 306 def imm16ShiftedZExt : PatLeaf<(imm), [{ 307 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 308 // immediate are set. Used by instructions like 'xoris'. 309 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 310 }], HI16>; 311 312 def imm16ShiftedSExt : PatLeaf<(imm), [{ 313 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 314 // immediate are set. Used by instructions like 'addis'. Identical to 315 // imm16ShiftedZExt in 32-bit mode. 316 if (N->getZExtValue() & 0xFFFF) return false; 317 if (N->getValueType(0) == MVT::i32) 318 return true; 319 // For 64-bit, make sure it is sext right. 320 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 321 }], HI16>; 322 323 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 324 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 325 // zero extended field. 326 return isUInt<32>(Imm); 327 }]>; 328 329 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 330 // restricted memrix (4-aligned) constants are alignment sensitive. If these 331 // offsets are hidden behind TOC entries than the values of the lower-order 332 // bits cannot be checked directly. As a result, we need to also incorporate 333 // an alignment check into the relevant patterns. 334 335 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 336 return cast<LoadSDNode>(N)->getAlignment() >= 4; 337 }]>; 338 def aligned4store : PatFrag<(ops node:$val, node:$ptr), 339 (store node:$val, node:$ptr), [{ 340 return cast<StoreSDNode>(N)->getAlignment() >= 4; 341 }]>; 342 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 343 return cast<LoadSDNode>(N)->getAlignment() >= 4; 344 }]>; 345 def aligned4pre_store : PatFrag< 346 (ops node:$val, node:$base, node:$offset), 347 (pre_store node:$val, node:$base, node:$offset), [{ 348 return cast<StoreSDNode>(N)->getAlignment() >= 4; 349 }]>; 350 351 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 352 return cast<LoadSDNode>(N)->getAlignment() < 4; 353 }]>; 354 def unaligned4store : PatFrag<(ops node:$val, node:$ptr), 355 (store node:$val, node:$ptr), [{ 356 return cast<StoreSDNode>(N)->getAlignment() < 4; 357 }]>; 358 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 359 return cast<LoadSDNode>(N)->getAlignment() < 4; 360 }]>; 361 362 //===----------------------------------------------------------------------===// 363 // PowerPC Flag Definitions. 364 365 class isPPC64 { bit PPC64 = 1; } 366 class isDOT { bit RC = 1; } 367 368 class RegConstraint<string C> { 369 string Constraints = C; 370 } 371 class NoEncode<string E> { 372 string DisableEncoding = E; 373 } 374 375 376 //===----------------------------------------------------------------------===// 377 // PowerPC Operand Definitions. 378 379 // In the default PowerPC assembler syntax, registers are specified simply 380 // by number, so they cannot be distinguished from immediate values (without 381 // looking at the opcode). This means that the default operand matching logic 382 // for the asm parser does not work, and we need to specify custom matchers. 383 // Since those can only be specified with RegisterOperand classes and not 384 // directly on the RegisterClass, all instructions patterns used by the asm 385 // parser need to use a RegisterOperand (instead of a RegisterClass) for 386 // all their register operands. 387 // For this purpose, we define one RegisterOperand for each RegisterClass, 388 // using the same name as the class, just in lower case. 389 390 def PPCRegGPRCAsmOperand : AsmOperandClass { 391 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 392 } 393 def gprc : RegisterOperand<GPRC> { 394 let ParserMatchClass = PPCRegGPRCAsmOperand; 395 } 396 def PPCRegG8RCAsmOperand : AsmOperandClass { 397 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 398 } 399 def g8rc : RegisterOperand<G8RC> { 400 let ParserMatchClass = PPCRegG8RCAsmOperand; 401 } 402 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 403 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 404 } 405 def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 406 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 407 } 408 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 409 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 410 } 411 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 412 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 413 } 414 def PPCRegF8RCAsmOperand : AsmOperandClass { 415 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 416 } 417 def f8rc : RegisterOperand<F8RC> { 418 let ParserMatchClass = PPCRegF8RCAsmOperand; 419 } 420 def PPCRegF4RCAsmOperand : AsmOperandClass { 421 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 422 } 423 def f4rc : RegisterOperand<F4RC> { 424 let ParserMatchClass = PPCRegF4RCAsmOperand; 425 } 426 def PPCRegVRRCAsmOperand : AsmOperandClass { 427 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 428 } 429 def vrrc : RegisterOperand<VRRC> { 430 let ParserMatchClass = PPCRegVRRCAsmOperand; 431 } 432 def PPCRegCRBITRCAsmOperand : AsmOperandClass { 433 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 434 } 435 def crbitrc : RegisterOperand<CRBITRC> { 436 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 437 } 438 def PPCRegCRRCAsmOperand : AsmOperandClass { 439 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 440 } 441 def crrc : RegisterOperand<CRRC> { 442 let ParserMatchClass = PPCRegCRRCAsmOperand; 443 } 444 def crrc0 : RegisterOperand<CRRC0> { 445 let ParserMatchClass = PPCRegCRRCAsmOperand; 446 } 447 448 def PPCU1ImmAsmOperand : AsmOperandClass { 449 let Name = "U1Imm"; let PredicateMethod = "isU1Imm"; 450 let RenderMethod = "addImmOperands"; 451 } 452 def u1imm : Operand<i32> { 453 let PrintMethod = "printU1ImmOperand"; 454 let ParserMatchClass = PPCU1ImmAsmOperand; 455 } 456 457 def PPCU2ImmAsmOperand : AsmOperandClass { 458 let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; 459 let RenderMethod = "addImmOperands"; 460 } 461 def u2imm : Operand<i32> { 462 let PrintMethod = "printU2ImmOperand"; 463 let ParserMatchClass = PPCU2ImmAsmOperand; 464 } 465 466 def PPCU3ImmAsmOperand : AsmOperandClass { 467 let Name = "U3Imm"; let PredicateMethod = "isU3Imm"; 468 let RenderMethod = "addImmOperands"; 469 } 470 def u3imm : Operand<i32> { 471 let PrintMethod = "printU3ImmOperand"; 472 let ParserMatchClass = PPCU3ImmAsmOperand; 473 } 474 475 def PPCU4ImmAsmOperand : AsmOperandClass { 476 let Name = "U4Imm"; let PredicateMethod = "isU4Imm"; 477 let RenderMethod = "addImmOperands"; 478 } 479 def u4imm : Operand<i32> { 480 let PrintMethod = "printU4ImmOperand"; 481 let ParserMatchClass = PPCU4ImmAsmOperand; 482 } 483 def PPCS5ImmAsmOperand : AsmOperandClass { 484 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 485 let RenderMethod = "addImmOperands"; 486 } 487 def s5imm : Operand<i32> { 488 let PrintMethod = "printS5ImmOperand"; 489 let ParserMatchClass = PPCS5ImmAsmOperand; 490 let DecoderMethod = "decodeSImmOperand<5>"; 491 } 492 def PPCU5ImmAsmOperand : AsmOperandClass { 493 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 494 let RenderMethod = "addImmOperands"; 495 } 496 def u5imm : Operand<i32> { 497 let PrintMethod = "printU5ImmOperand"; 498 let ParserMatchClass = PPCU5ImmAsmOperand; 499 let DecoderMethod = "decodeUImmOperand<5>"; 500 } 501 def PPCU6ImmAsmOperand : AsmOperandClass { 502 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 503 let RenderMethod = "addImmOperands"; 504 } 505 def u6imm : Operand<i32> { 506 let PrintMethod = "printU6ImmOperand"; 507 let ParserMatchClass = PPCU6ImmAsmOperand; 508 let DecoderMethod = "decodeUImmOperand<6>"; 509 } 510 def PPCU10ImmAsmOperand : AsmOperandClass { 511 let Name = "U10Imm"; let PredicateMethod = "isU10Imm"; 512 let RenderMethod = "addImmOperands"; 513 } 514 def u10imm : Operand<i32> { 515 let PrintMethod = "printU10ImmOperand"; 516 let ParserMatchClass = PPCU10ImmAsmOperand; 517 let DecoderMethod = "decodeUImmOperand<10>"; 518 } 519 def PPCU12ImmAsmOperand : AsmOperandClass { 520 let Name = "U12Imm"; let PredicateMethod = "isU12Imm"; 521 let RenderMethod = "addImmOperands"; 522 } 523 def u12imm : Operand<i32> { 524 let PrintMethod = "printU12ImmOperand"; 525 let ParserMatchClass = PPCU12ImmAsmOperand; 526 let DecoderMethod = "decodeUImmOperand<12>"; 527 } 528 def PPCS16ImmAsmOperand : AsmOperandClass { 529 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 530 let RenderMethod = "addS16ImmOperands"; 531 } 532 def s16imm : Operand<i32> { 533 let PrintMethod = "printS16ImmOperand"; 534 let EncoderMethod = "getImm16Encoding"; 535 let ParserMatchClass = PPCS16ImmAsmOperand; 536 let DecoderMethod = "decodeSImmOperand<16>"; 537 } 538 def PPCU16ImmAsmOperand : AsmOperandClass { 539 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 540 let RenderMethod = "addU16ImmOperands"; 541 } 542 def u16imm : Operand<i32> { 543 let PrintMethod = "printU16ImmOperand"; 544 let EncoderMethod = "getImm16Encoding"; 545 let ParserMatchClass = PPCU16ImmAsmOperand; 546 let DecoderMethod = "decodeUImmOperand<16>"; 547 } 548 def PPCS17ImmAsmOperand : AsmOperandClass { 549 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 550 let RenderMethod = "addS16ImmOperands"; 551 } 552 def s17imm : Operand<i32> { 553 // This operand type is used for addis/lis to allow the assembler parser 554 // to accept immediates in the range -65536..65535 for compatibility with 555 // the GNU assembler. The operand is treated as 16-bit otherwise. 556 let PrintMethod = "printS16ImmOperand"; 557 let EncoderMethod = "getImm16Encoding"; 558 let ParserMatchClass = PPCS17ImmAsmOperand; 559 let DecoderMethod = "decodeSImmOperand<16>"; 560 } 561 def PPCDirectBrAsmOperand : AsmOperandClass { 562 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 563 let RenderMethod = "addBranchTargetOperands"; 564 } 565 def directbrtarget : Operand<OtherVT> { 566 let PrintMethod = "printBranchOperand"; 567 let EncoderMethod = "getDirectBrEncoding"; 568 let ParserMatchClass = PPCDirectBrAsmOperand; 569 } 570 def absdirectbrtarget : Operand<OtherVT> { 571 let PrintMethod = "printAbsBranchOperand"; 572 let EncoderMethod = "getAbsDirectBrEncoding"; 573 let ParserMatchClass = PPCDirectBrAsmOperand; 574 } 575 def PPCCondBrAsmOperand : AsmOperandClass { 576 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 577 let RenderMethod = "addBranchTargetOperands"; 578 } 579 def condbrtarget : Operand<OtherVT> { 580 let PrintMethod = "printBranchOperand"; 581 let EncoderMethod = "getCondBrEncoding"; 582 let ParserMatchClass = PPCCondBrAsmOperand; 583 } 584 def abscondbrtarget : Operand<OtherVT> { 585 let PrintMethod = "printAbsBranchOperand"; 586 let EncoderMethod = "getAbsCondBrEncoding"; 587 let ParserMatchClass = PPCCondBrAsmOperand; 588 } 589 def calltarget : Operand<iPTR> { 590 let PrintMethod = "printBranchOperand"; 591 let EncoderMethod = "getDirectBrEncoding"; 592 let ParserMatchClass = PPCDirectBrAsmOperand; 593 } 594 def abscalltarget : Operand<iPTR> { 595 let PrintMethod = "printAbsBranchOperand"; 596 let EncoderMethod = "getAbsDirectBrEncoding"; 597 let ParserMatchClass = PPCDirectBrAsmOperand; 598 } 599 def PPCCRBitMaskOperand : AsmOperandClass { 600 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 601 } 602 def crbitm: Operand<i8> { 603 let PrintMethod = "printcrbitm"; 604 let EncoderMethod = "get_crbitm_encoding"; 605 let DecoderMethod = "decodeCRBitMOperand"; 606 let ParserMatchClass = PPCCRBitMaskOperand; 607 } 608 // Address operands 609 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 610 def PPCRegGxRCNoR0Operand : AsmOperandClass { 611 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 612 } 613 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 614 let ParserMatchClass = PPCRegGxRCNoR0Operand; 615 } 616 // A version of ptr_rc usable with the asm parser. 617 def PPCRegGxRCOperand : AsmOperandClass { 618 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 619 } 620 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 621 let ParserMatchClass = PPCRegGxRCOperand; 622 } 623 624 def PPCDispRIOperand : AsmOperandClass { 625 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 626 let RenderMethod = "addS16ImmOperands"; 627 } 628 def dispRI : Operand<iPTR> { 629 let ParserMatchClass = PPCDispRIOperand; 630 } 631 def PPCDispRIXOperand : AsmOperandClass { 632 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 633 let RenderMethod = "addImmOperands"; 634 } 635 def dispRIX : Operand<iPTR> { 636 let ParserMatchClass = PPCDispRIXOperand; 637 } 638 def PPCDispSPE8Operand : AsmOperandClass { 639 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8"; 640 let RenderMethod = "addImmOperands"; 641 } 642 def dispSPE8 : Operand<iPTR> { 643 let ParserMatchClass = PPCDispSPE8Operand; 644 } 645 def PPCDispSPE4Operand : AsmOperandClass { 646 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4"; 647 let RenderMethod = "addImmOperands"; 648 } 649 def dispSPE4 : Operand<iPTR> { 650 let ParserMatchClass = PPCDispSPE4Operand; 651 } 652 def PPCDispSPE2Operand : AsmOperandClass { 653 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2"; 654 let RenderMethod = "addImmOperands"; 655 } 656 def dispSPE2 : Operand<iPTR> { 657 let ParserMatchClass = PPCDispSPE2Operand; 658 } 659 660 def memri : Operand<iPTR> { 661 let PrintMethod = "printMemRegImm"; 662 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 663 let EncoderMethod = "getMemRIEncoding"; 664 let DecoderMethod = "decodeMemRIOperands"; 665 } 666 def memrr : Operand<iPTR> { 667 let PrintMethod = "printMemRegReg"; 668 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 669 } 670 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 671 let PrintMethod = "printMemRegImm"; 672 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 673 let EncoderMethod = "getMemRIXEncoding"; 674 let DecoderMethod = "decodeMemRIXOperands"; 675 } 676 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned. 677 let PrintMethod = "printMemRegImm"; 678 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 679 let EncoderMethod = "getSPE8DisEncoding"; 680 } 681 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned. 682 let PrintMethod = "printMemRegImm"; 683 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 684 let EncoderMethod = "getSPE4DisEncoding"; 685 } 686 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned. 687 let PrintMethod = "printMemRegImm"; 688 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 689 let EncoderMethod = "getSPE2DisEncoding"; 690 } 691 692 // A single-register address. This is used with the SjLj 693 // pseudo-instructions. 694 def memr : Operand<iPTR> { 695 let MIOperandInfo = (ops ptr_rc:$ptrreg); 696 } 697 def PPCTLSRegOperand : AsmOperandClass { 698 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 699 let RenderMethod = "addTLSRegOperands"; 700 } 701 def tlsreg32 : Operand<i32> { 702 let EncoderMethod = "getTLSRegEncoding"; 703 let ParserMatchClass = PPCTLSRegOperand; 704 } 705 def tlsgd32 : Operand<i32> {} 706 def tlscall32 : Operand<i32> { 707 let PrintMethod = "printTLSCall"; 708 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym); 709 let EncoderMethod = "getTLSCallEncoding"; 710 } 711 712 // PowerPC Predicate operand. 713 def pred : Operand<OtherVT> { 714 let PrintMethod = "printPredicateOperand"; 715 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 716 } 717 718 // Define PowerPC specific addressing mode. 719 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 720 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 721 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 722 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 723 724 // The address in a single register. This is used with the SjLj 725 // pseudo-instructions. 726 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 727 728 /// This is just the offset part of iaddr, used for preinc. 729 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 730 731 //===----------------------------------------------------------------------===// 732 // PowerPC Instruction Predicate Definitions. 733 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">; 734 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">; 735 def IsBookE : Predicate<"PPCSubTarget->isBookE()">; 736 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">; 737 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">; 738 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">; 739 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">; 740 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">; 741 def IsE500 : Predicate<"PPCSubTarget->isE500()">; 742 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">; 743 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">; 744 def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">; 745 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; 746 def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">; 747 def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">; 748 def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">; 749 750 //===----------------------------------------------------------------------===// 751 // PowerPC Multiclass Definitions. 752 753 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 754 string asmbase, string asmstr, InstrItinClass itin, 755 list<dag> pattern> { 756 let BaseName = asmbase in { 757 def NAME : XForm_6<opcode, xo, OOL, IOL, 758 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 759 pattern>, RecFormRel; 760 let Defs = [CR0] in 761 def o : XForm_6<opcode, xo, OOL, IOL, 762 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 763 []>, isDOT, RecFormRel; 764 } 765 } 766 767 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 768 string asmbase, string asmstr, InstrItinClass itin, 769 list<dag> pattern> { 770 let BaseName = asmbase in { 771 let Defs = [CARRY] in 772 def NAME : XForm_6<opcode, xo, OOL, IOL, 773 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 774 pattern>, RecFormRel; 775 let Defs = [CARRY, CR0] in 776 def o : XForm_6<opcode, xo, OOL, IOL, 777 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 778 []>, isDOT, RecFormRel; 779 } 780 } 781 782 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 783 string asmbase, string asmstr, InstrItinClass itin, 784 list<dag> pattern> { 785 let BaseName = asmbase in { 786 let Defs = [CARRY] in 787 def NAME : XForm_10<opcode, xo, OOL, IOL, 788 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 789 pattern>, RecFormRel; 790 let Defs = [CARRY, CR0] in 791 def o : XForm_10<opcode, xo, OOL, IOL, 792 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 793 []>, isDOT, RecFormRel; 794 } 795 } 796 797 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 798 string asmbase, string asmstr, InstrItinClass itin, 799 list<dag> pattern> { 800 let BaseName = asmbase in { 801 def NAME : XForm_11<opcode, xo, OOL, IOL, 802 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 803 pattern>, RecFormRel; 804 let Defs = [CR0] in 805 def o : XForm_11<opcode, xo, OOL, IOL, 806 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 807 []>, isDOT, RecFormRel; 808 } 809 } 810 811 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 812 string asmbase, string asmstr, InstrItinClass itin, 813 list<dag> pattern> { 814 let BaseName = asmbase in { 815 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 816 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 817 pattern>, RecFormRel; 818 let Defs = [CR0] in 819 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 820 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 821 []>, isDOT, RecFormRel; 822 } 823 } 824 825 // Multiclass for instructions for which the non record form is not cracked 826 // and the record form is cracked (i.e. divw, mullw, etc.) 827 multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 828 string asmbase, string asmstr, InstrItinClass itin, 829 list<dag> pattern> { 830 let BaseName = asmbase in { 831 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 832 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 833 pattern>, RecFormRel; 834 let Defs = [CR0] in 835 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 836 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 837 []>, isDOT, RecFormRel, PPC970_DGroup_First, 838 PPC970_DGroup_Cracked; 839 } 840 } 841 842 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 843 string asmbase, string asmstr, InstrItinClass itin, 844 list<dag> pattern> { 845 let BaseName = asmbase in { 846 let Defs = [CARRY] in 847 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 848 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 849 pattern>, RecFormRel; 850 let Defs = [CARRY, CR0] in 851 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 852 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 853 []>, isDOT, RecFormRel; 854 } 855 } 856 857 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 858 string asmbase, string asmstr, InstrItinClass itin, 859 list<dag> pattern> { 860 let BaseName = asmbase in { 861 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 862 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 863 pattern>, RecFormRel; 864 let Defs = [CR0] in 865 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 866 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 867 []>, isDOT, RecFormRel; 868 } 869 } 870 871 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 872 string asmbase, string asmstr, InstrItinClass itin, 873 list<dag> pattern> { 874 let BaseName = asmbase in { 875 let Defs = [CARRY] in 876 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 877 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 878 pattern>, RecFormRel; 879 let Defs = [CARRY, CR0] in 880 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 881 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 882 []>, isDOT, RecFormRel; 883 } 884 } 885 886 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 887 string asmbase, string asmstr, InstrItinClass itin, 888 list<dag> pattern> { 889 let BaseName = asmbase in { 890 def NAME : MForm_2<opcode, OOL, IOL, 891 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 892 pattern>, RecFormRel; 893 let Defs = [CR0] in 894 def o : MForm_2<opcode, OOL, IOL, 895 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 896 []>, isDOT, RecFormRel; 897 } 898 } 899 900 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 901 string asmbase, string asmstr, InstrItinClass itin, 902 list<dag> pattern> { 903 let BaseName = asmbase in { 904 def NAME : MDForm_1<opcode, xo, OOL, IOL, 905 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 906 pattern>, RecFormRel; 907 let Defs = [CR0] in 908 def o : MDForm_1<opcode, xo, OOL, IOL, 909 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 910 []>, isDOT, RecFormRel; 911 } 912 } 913 914 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 915 string asmbase, string asmstr, InstrItinClass itin, 916 list<dag> pattern> { 917 let BaseName = asmbase in { 918 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 919 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 920 pattern>, RecFormRel; 921 let Defs = [CR0] in 922 def o : MDSForm_1<opcode, xo, OOL, IOL, 923 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 924 []>, isDOT, RecFormRel; 925 } 926 } 927 928 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 929 string asmbase, string asmstr, InstrItinClass itin, 930 list<dag> pattern> { 931 let BaseName = asmbase in { 932 let Defs = [CARRY] in 933 def NAME : XSForm_1<opcode, xo, OOL, IOL, 934 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 935 pattern>, RecFormRel; 936 let Defs = [CARRY, CR0] in 937 def o : XSForm_1<opcode, xo, OOL, IOL, 938 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 939 []>, isDOT, RecFormRel; 940 } 941 } 942 943 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 944 string asmbase, string asmstr, InstrItinClass itin, 945 list<dag> pattern> { 946 let BaseName = asmbase in { 947 def NAME : XForm_26<opcode, xo, OOL, IOL, 948 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 949 pattern>, RecFormRel; 950 let Defs = [CR1] in 951 def o : XForm_26<opcode, xo, OOL, IOL, 952 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 953 []>, isDOT, RecFormRel; 954 } 955 } 956 957 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 958 string asmbase, string asmstr, InstrItinClass itin, 959 list<dag> pattern> { 960 let BaseName = asmbase in { 961 def NAME : XForm_28<opcode, xo, OOL, IOL, 962 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 963 pattern>, RecFormRel; 964 let Defs = [CR1] in 965 def o : XForm_28<opcode, xo, OOL, IOL, 966 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 967 []>, isDOT, RecFormRel; 968 } 969 } 970 971 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 972 string asmbase, string asmstr, InstrItinClass itin, 973 list<dag> pattern> { 974 let BaseName = asmbase in { 975 def NAME : AForm_1<opcode, xo, OOL, IOL, 976 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 977 pattern>, RecFormRel; 978 let Defs = [CR1] in 979 def o : AForm_1<opcode, xo, OOL, IOL, 980 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 981 []>, isDOT, RecFormRel; 982 } 983 } 984 985 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 986 string asmbase, string asmstr, InstrItinClass itin, 987 list<dag> pattern> { 988 let BaseName = asmbase in { 989 def NAME : AForm_2<opcode, xo, OOL, IOL, 990 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 991 pattern>, RecFormRel; 992 let Defs = [CR1] in 993 def o : AForm_2<opcode, xo, OOL, IOL, 994 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 995 []>, isDOT, RecFormRel; 996 } 997 } 998 999 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1000 string asmbase, string asmstr, InstrItinClass itin, 1001 list<dag> pattern> { 1002 let BaseName = asmbase in { 1003 def NAME : AForm_3<opcode, xo, OOL, IOL, 1004 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1005 pattern>, RecFormRel; 1006 let Defs = [CR1] in 1007 def o : AForm_3<opcode, xo, OOL, IOL, 1008 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1009 []>, isDOT, RecFormRel; 1010 } 1011 } 1012 1013 //===----------------------------------------------------------------------===// 1014 // PowerPC Instruction Definitions. 1015 1016 // Pseudo-instructions: 1017 1018 let hasCtrlDep = 1 in { 1019 let Defs = [R1], Uses = [R1] in { 1020 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt", 1021 [(callseq_start timm:$amt)]>; 1022 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2", 1023 [(callseq_end timm:$amt1, timm:$amt2)]>; 1024 } 1025 1026 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS), 1027 "UPDATE_VRSAVE $rD, $rS", []>; 1028 } 1029 1030 let Defs = [R1], Uses = [R1] in 1031 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1032 [(set i32:$result, 1033 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1034 def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1035 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1036 1037 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1038 // instruction selection into a branch sequence. 1039 let usesCustomInserter = 1, // Expanded after instruction selection. 1040 PPC970_Single = 1 in { 1041 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1042 // because either operand might become the first operand in an isel, and 1043 // that operand cannot be r0. 1044 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond, 1045 gprc_nor0:$T, gprc_nor0:$F, 1046 i32imm:$BROPC), "#SELECT_CC_I4", 1047 []>; 1048 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond, 1049 g8rc_nox0:$T, g8rc_nox0:$F, 1050 i32imm:$BROPC), "#SELECT_CC_I8", 1051 []>; 1052 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1053 i32imm:$BROPC), "#SELECT_CC_F4", 1054 []>; 1055 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1056 i32imm:$BROPC), "#SELECT_CC_F8", 1057 []>; 1058 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1059 i32imm:$BROPC), "#SELECT_CC_VRRC", 1060 []>; 1061 1062 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1063 // register bit directly. 1064 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1065 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1066 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1067 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1068 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1069 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1070 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1071 f4rc:$T, f4rc:$F), "#SELECT_F4", 1072 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1073 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1074 f8rc:$T, f8rc:$F), "#SELECT_F8", 1075 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1076 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1077 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1078 [(set v4i32:$dst, 1079 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1080 } 1081 1082 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1083 // scavenge a register for it. 1084 let mayStore = 1 in { 1085 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F), 1086 "#SPILL_CR", []>; 1087 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F), 1088 "#SPILL_CRBIT", []>; 1089 } 1090 1091 // RESTORE_CR - Indicate that we're restoring the CR register (previously 1092 // spilled), so we'll need to scavenge a register for it. 1093 let mayLoad = 1 in { 1094 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F), 1095 "#RESTORE_CR", []>; 1096 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F), 1097 "#RESTORE_CRBIT", []>; 1098 } 1099 1100 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 1101 let isReturn = 1, Uses = [LR, RM] in 1102 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1103 [(retflag)]>, Requires<[In32BitMode]>; 1104 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1105 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1106 []>; 1107 1108 let isCodeGenOnly = 1 in { 1109 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 1110 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1111 []>; 1112 1113 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 1114 "bcctr 12, $bi, 0", IIC_BrB, []>; 1115 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 1116 "bcctr 4, $bi, 0", IIC_BrB, []>; 1117 } 1118 } 1119 } 1120 1121 let Defs = [LR] in 1122 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>, 1123 PPC970_Unit_BRU; 1124 let Defs = [LR] in 1125 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1126 PPC970_Unit_BRU; 1127 1128 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 1129 let isBarrier = 1 in { 1130 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 1131 "b $dst", IIC_BrB, 1132 [(br bb:$dst)]>; 1133 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 1134 "ba $dst", IIC_BrB, []>; 1135 } 1136 1137 // BCC represents an arbitrary conditional branch on a predicate. 1138 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1139 // a two-value operand where a dag node expects two operands. :( 1140 let isCodeGenOnly = 1 in { 1141 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 1142 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 1143 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 1144 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1145 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 1146 1147 let isReturn = 1, Uses = [LR, RM] in 1148 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 1149 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1150 } 1151 1152 let isCodeGenOnly = 1 in { 1153 let Pattern = [(brcond i1:$bi, bb:$dst)] in 1154 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1155 "bc 12, $bi, $dst">; 1156 1157 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in 1158 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1159 "bc 4, $bi, $dst">; 1160 1161 let isReturn = 1, Uses = [LR, RM] in 1162 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), 1163 "bclr 12, $bi, 0", IIC_BrB, []>; 1164 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), 1165 "bclr 4, $bi, 0", IIC_BrB, []>; 1166 } 1167 1168 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1169 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1170 "bdzlr", IIC_BrB, []>; 1171 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1172 "bdnzlr", IIC_BrB, []>; 1173 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1174 "bdzlr+", IIC_BrB, []>; 1175 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1176 "bdnzlr+", IIC_BrB, []>; 1177 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1178 "bdzlr-", IIC_BrB, []>; 1179 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1180 "bdnzlr-", IIC_BrB, []>; 1181 } 1182 1183 let Defs = [CTR], Uses = [CTR] in { 1184 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 1185 "bdz $dst">; 1186 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 1187 "bdnz $dst">; 1188 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 1189 "bdza $dst">; 1190 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 1191 "bdnza $dst">; 1192 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 1193 "bdz+ $dst">; 1194 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 1195 "bdnz+ $dst">; 1196 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 1197 "bdza+ $dst">; 1198 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 1199 "bdnza+ $dst">; 1200 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 1201 "bdz- $dst">; 1202 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 1203 "bdnz- $dst">; 1204 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 1205 "bdza- $dst">; 1206 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 1207 "bdnza- $dst">; 1208 } 1209 } 1210 1211 // The unconditional BCL used by the SjLj setjmp code. 1212 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in { 1213 let Defs = [LR], Uses = [RM] in { 1214 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 1215 "bcl 20, 31, $dst">; 1216 } 1217 } 1218 1219 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1220 // Convenient aliases for call instructions 1221 let Uses = [RM] in { 1222 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1223 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1224 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1225 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; 1226 1227 let isCodeGenOnly = 1 in { 1228 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), 1229 "bl $func", IIC_BrB, []>; 1230 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 1231 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 1232 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1233 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 1234 1235 def BCL : BForm_4<16, 12, 0, 1, (outs), 1236 (ins crbitrc:$bi, condbrtarget:$dst), 1237 "bcl 12, $bi, $dst">; 1238 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1239 (ins crbitrc:$bi, condbrtarget:$dst), 1240 "bcl 4, $bi, $dst">; 1241 } 1242 } 1243 let Uses = [CTR, RM] in { 1244 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1245 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1246 Requires<[In32BitMode]>; 1247 1248 let isCodeGenOnly = 1 in { 1249 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1250 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1251 []>; 1252 1253 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 1254 "bcctrl 12, $bi, 0", IIC_BrB, []>; 1255 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 1256 "bcctrl 4, $bi, 0", IIC_BrB, []>; 1257 } 1258 } 1259 let Uses = [LR, RM] in { 1260 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1261 "blrl", IIC_BrB, []>; 1262 1263 let isCodeGenOnly = 1 in { 1264 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1265 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1266 []>; 1267 1268 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), 1269 "bclrl 12, $bi, 0", IIC_BrB, []>; 1270 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), 1271 "bclrl 4, $bi, 0", IIC_BrB, []>; 1272 } 1273 } 1274 let Defs = [CTR], Uses = [CTR, RM] in { 1275 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1276 "bdzl $dst">; 1277 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1278 "bdnzl $dst">; 1279 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1280 "bdzla $dst">; 1281 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1282 "bdnzla $dst">; 1283 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1284 "bdzl+ $dst">; 1285 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1286 "bdnzl+ $dst">; 1287 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1288 "bdzla+ $dst">; 1289 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1290 "bdnzla+ $dst">; 1291 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1292 "bdzl- $dst">; 1293 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1294 "bdnzl- $dst">; 1295 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1296 "bdzla- $dst">; 1297 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1298 "bdnzla- $dst">; 1299 } 1300 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1301 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1302 "bdzlrl", IIC_BrB, []>; 1303 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1304 "bdnzlrl", IIC_BrB, []>; 1305 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1306 "bdzlrl+", IIC_BrB, []>; 1307 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1308 "bdnzlrl+", IIC_BrB, []>; 1309 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1310 "bdzlrl-", IIC_BrB, []>; 1311 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1312 "bdnzlrl-", IIC_BrB, []>; 1313 } 1314 } 1315 1316 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1317 def TCRETURNdi :Pseudo< (outs), 1318 (ins calltarget:$dst, i32imm:$offset), 1319 "#TC_RETURNd $dst $offset", 1320 []>; 1321 1322 1323 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1324 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1325 "#TC_RETURNa $func $offset", 1326 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1327 1328 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1329 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1330 "#TC_RETURNr $dst $offset", 1331 []>; 1332 1333 1334 let isCodeGenOnly = 1 in { 1335 1336 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1337 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1338 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1339 []>, Requires<[In32BitMode]>; 1340 1341 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1342 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1343 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1344 "b $dst", IIC_BrB, 1345 []>; 1346 1347 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1348 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1349 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1350 "ba $dst", IIC_BrB, 1351 []>; 1352 1353 } 1354 1355 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 1356 let Defs = [CTR] in 1357 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 1358 "#EH_SJLJ_SETJMP32", 1359 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1360 Requires<[In32BitMode]>; 1361 let isTerminator = 1 in 1362 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf), 1363 "#EH_SJLJ_LONGJMP32", 1364 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1365 Requires<[In32BitMode]>; 1366 } 1367 1368 let isBranch = 1, isTerminator = 1 in { 1369 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst), 1370 "#EH_SjLj_Setup\t$dst", []>; 1371 } 1372 1373 // System call. 1374 let PPC970_Unit = 7 in { 1375 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 1376 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; 1377 } 1378 1379 // Branch history rolling buffer. 1380 def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1381 [(PPCclrbhrb)]>, 1382 PPC970_DGroup_Single; 1383 // The $dmy argument used for MFBHRBE is not needed; however, including 1384 // it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1385 // interferes with necessary special handling (see PPCFastISel.cpp). 1386 def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), 1387 (ins u10imm:$imm, u10imm:$dmy), 1388 "mfbhrbe $rD, $imm", IIC_BrB, 1389 [(set i32:$rD, 1390 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1391 PPC970_DGroup_First; 1392 1393 def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", 1394 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, 1395 PPC970_DGroup_Single; 1396 1397 // DCB* instructions. 1398 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", 1399 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 1400 PPC970_DGroup_Single; 1401 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst", 1402 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 1403 PPC970_DGroup_Single; 1404 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", 1405 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 1406 PPC970_DGroup_Single; 1407 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", 1408 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 1409 PPC970_DGroup_Single; 1410 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", 1411 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 1412 PPC970_DGroup_Single; 1413 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", 1414 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 1415 PPC970_DGroup_Single; 1416 1417 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1418 def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), 1419 "dcbt $dst, $TH", IIC_LdStDCBF, []>, 1420 PPC970_DGroup_Single; 1421 def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), 1422 "dcbtst $dst, $TH", IIC_LdStDCBF, []>, 1423 PPC970_DGroup_Single; 1424 } // hasSideEffects = 0 1425 1426 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), 1427 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1428 1429 def : Pat<(int_ppc_dcbt xoaddr:$dst), 1430 (DCBT 0, xoaddr:$dst)>; 1431 def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1432 (DCBTST 0, xoaddr:$dst)>; 1433 1434 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 1435 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1436 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), 1437 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1438 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), 1439 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1440 1441 // Atomic operations 1442 let usesCustomInserter = 1 in { 1443 let Defs = [CR0] in { 1444 def ATOMIC_LOAD_ADD_I8 : Pseudo< 1445 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1446 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>; 1447 def ATOMIC_LOAD_SUB_I8 : Pseudo< 1448 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1449 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>; 1450 def ATOMIC_LOAD_AND_I8 : Pseudo< 1451 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1452 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>; 1453 def ATOMIC_LOAD_OR_I8 : Pseudo< 1454 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1455 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>; 1456 def ATOMIC_LOAD_XOR_I8 : Pseudo< 1457 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1458 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>; 1459 def ATOMIC_LOAD_NAND_I8 : Pseudo< 1460 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1461 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>; 1462 def ATOMIC_LOAD_ADD_I16 : Pseudo< 1463 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1464 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>; 1465 def ATOMIC_LOAD_SUB_I16 : Pseudo< 1466 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1467 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>; 1468 def ATOMIC_LOAD_AND_I16 : Pseudo< 1469 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1470 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>; 1471 def ATOMIC_LOAD_OR_I16 : Pseudo< 1472 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1473 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>; 1474 def ATOMIC_LOAD_XOR_I16 : Pseudo< 1475 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1476 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>; 1477 def ATOMIC_LOAD_NAND_I16 : Pseudo< 1478 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1479 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>; 1480 def ATOMIC_LOAD_ADD_I32 : Pseudo< 1481 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1482 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>; 1483 def ATOMIC_LOAD_SUB_I32 : Pseudo< 1484 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1485 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>; 1486 def ATOMIC_LOAD_AND_I32 : Pseudo< 1487 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1488 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>; 1489 def ATOMIC_LOAD_OR_I32 : Pseudo< 1490 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1491 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>; 1492 def ATOMIC_LOAD_XOR_I32 : Pseudo< 1493 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1494 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>; 1495 def ATOMIC_LOAD_NAND_I32 : Pseudo< 1496 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1497 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>; 1498 1499 def ATOMIC_CMP_SWAP_I8 : Pseudo< 1500 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1501 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>; 1502 def ATOMIC_CMP_SWAP_I16 : Pseudo< 1503 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1504 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>; 1505 def ATOMIC_CMP_SWAP_I32 : Pseudo< 1506 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1507 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>; 1508 1509 def ATOMIC_SWAP_I8 : Pseudo< 1510 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1511 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>; 1512 def ATOMIC_SWAP_I16 : Pseudo< 1513 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1514 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>; 1515 def ATOMIC_SWAP_I32 : Pseudo< 1516 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1517 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>; 1518 } 1519 } 1520 1521 // Instructions to support atomic operations 1522 let mayLoad = 1, hasSideEffects = 0 in { 1523 def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src), 1524 "lbarx $rD, $src", IIC_LdStLWARX, []>, 1525 Requires<[HasPartwordAtomics]>; 1526 1527 def LHARX : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src), 1528 "lharx $rD, $src", IIC_LdStLWARX, []>, 1529 Requires<[HasPartwordAtomics]>; 1530 1531 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src), 1532 "lwarx $rD, $src", IIC_LdStLWARX, []>; 1533 1534 // Instructions to support lock versions of atomics 1535 // (EH=1 - see Power ISA 2.07 Book II 4.4.2) 1536 def LBARXL : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src), 1537 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT, 1538 Requires<[HasPartwordAtomics]>; 1539 1540 def LHARXL : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src), 1541 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT, 1542 Requires<[HasPartwordAtomics]>; 1543 1544 def LWARXL : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src), 1545 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT; 1546 } 1547 1548 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in { 1549 def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst), 1550 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>, 1551 isDOT, Requires<[HasPartwordAtomics]>; 1552 1553 def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst), 1554 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>, 1555 isDOT, Requires<[HasPartwordAtomics]>; 1556 1557 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 1558 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT; 1559 } 1560 1561 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 1562 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1563 1564 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 1565 "twi $to, $rA, $imm", IIC_IntTrapW, []>; 1566 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 1567 "tw $to, $rA, $rB", IIC_IntTrapW, []>; 1568 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 1569 "tdi $to, $rA, $imm", IIC_IntTrapD, []>; 1570 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 1571 "td $to, $rA, $rB", IIC_IntTrapD, []>; 1572 1573 //===----------------------------------------------------------------------===// 1574 // PPC32 Load Instructions. 1575 // 1576 1577 // Unindexed (r+i) Loads. 1578 let PPC970_Unit = 2 in { 1579 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 1580 "lbz $rD, $src", IIC_LdStLoad, 1581 [(set i32:$rD, (zextloadi8 iaddr:$src))]>; 1582 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 1583 "lha $rD, $src", IIC_LdStLHA, 1584 [(set i32:$rD, (sextloadi16 iaddr:$src))]>, 1585 PPC970_DGroup_Cracked; 1586 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 1587 "lhz $rD, $src", IIC_LdStLoad, 1588 [(set i32:$rD, (zextloadi16 iaddr:$src))]>; 1589 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 1590 "lwz $rD, $src", IIC_LdStLoad, 1591 [(set i32:$rD, (load iaddr:$src))]>; 1592 1593 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 1594 "lfs $rD, $src", IIC_LdStLFD, 1595 [(set f32:$rD, (load iaddr:$src))]>; 1596 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 1597 "lfd $rD, $src", IIC_LdStLFD, 1598 [(set f64:$rD, (load iaddr:$src))]>; 1599 1600 1601 // Unindexed (r+i) Loads with Update (preinc). 1602 let mayLoad = 1, hasSideEffects = 0 in { 1603 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1604 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1605 []>, RegConstraint<"$addr.reg = $ea_result">, 1606 NoEncode<"$ea_result">; 1607 1608 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1609 "lhau $rD, $addr", IIC_LdStLHAU, 1610 []>, RegConstraint<"$addr.reg = $ea_result">, 1611 NoEncode<"$ea_result">; 1612 1613 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1614 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1615 []>, RegConstraint<"$addr.reg = $ea_result">, 1616 NoEncode<"$ea_result">; 1617 1618 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1619 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1620 []>, RegConstraint<"$addr.reg = $ea_result">, 1621 NoEncode<"$ea_result">; 1622 1623 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1624 "lfsu $rD, $addr", IIC_LdStLFDU, 1625 []>, RegConstraint<"$addr.reg = $ea_result">, 1626 NoEncode<"$ea_result">; 1627 1628 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1629 "lfdu $rD, $addr", IIC_LdStLFDU, 1630 []>, RegConstraint<"$addr.reg = $ea_result">, 1631 NoEncode<"$ea_result">; 1632 1633 1634 // Indexed (r+r) Loads with Update (preinc). 1635 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1636 (ins memrr:$addr), 1637 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1638 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1639 NoEncode<"$ea_result">; 1640 1641 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1642 (ins memrr:$addr), 1643 "lhaux $rD, $addr", IIC_LdStLHAUX, 1644 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1645 NoEncode<"$ea_result">; 1646 1647 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1648 (ins memrr:$addr), 1649 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1650 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1651 NoEncode<"$ea_result">; 1652 1653 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1654 (ins memrr:$addr), 1655 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1656 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1657 NoEncode<"$ea_result">; 1658 1659 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 1660 (ins memrr:$addr), 1661 "lfsux $rD, $addr", IIC_LdStLFDUX, 1662 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1663 NoEncode<"$ea_result">; 1664 1665 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 1666 (ins memrr:$addr), 1667 "lfdux $rD, $addr", IIC_LdStLFDUX, 1668 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1669 NoEncode<"$ea_result">; 1670 } 1671 } 1672 1673 // Indexed (r+r) Loads. 1674 // 1675 let PPC970_Unit = 2 in { 1676 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src), 1677 "lbzx $rD, $src", IIC_LdStLoad, 1678 [(set i32:$rD, (zextloadi8 xaddr:$src))]>; 1679 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src), 1680 "lhax $rD, $src", IIC_LdStLHA, 1681 [(set i32:$rD, (sextloadi16 xaddr:$src))]>, 1682 PPC970_DGroup_Cracked; 1683 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src), 1684 "lhzx $rD, $src", IIC_LdStLoad, 1685 [(set i32:$rD, (zextloadi16 xaddr:$src))]>; 1686 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src), 1687 "lwzx $rD, $src", IIC_LdStLoad, 1688 [(set i32:$rD, (load xaddr:$src))]>; 1689 1690 1691 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src), 1692 "lhbrx $rD, $src", IIC_LdStLoad, 1693 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>; 1694 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src), 1695 "lwbrx $rD, $src", IIC_LdStLoad, 1696 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>; 1697 1698 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src), 1699 "lfsx $frD, $src", IIC_LdStLFD, 1700 [(set f32:$frD, (load xaddr:$src))]>; 1701 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src), 1702 "lfdx $frD, $src", IIC_LdStLFD, 1703 [(set f64:$frD, (load xaddr:$src))]>; 1704 1705 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src), 1706 "lfiwax $frD, $src", IIC_LdStLFD, 1707 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>; 1708 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src), 1709 "lfiwzx $frD, $src", IIC_LdStLFD, 1710 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>; 1711 } 1712 1713 // Load Multiple 1714 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 1715 "lmw $rD, $src", IIC_LdStLMW, []>; 1716 1717 //===----------------------------------------------------------------------===// 1718 // PPC32 Store Instructions. 1719 // 1720 1721 // Unindexed (r+i) Stores. 1722 let PPC970_Unit = 2 in { 1723 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src), 1724 "stb $rS, $src", IIC_LdStStore, 1725 [(truncstorei8 i32:$rS, iaddr:$src)]>; 1726 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src), 1727 "sth $rS, $src", IIC_LdStStore, 1728 [(truncstorei16 i32:$rS, iaddr:$src)]>; 1729 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src), 1730 "stw $rS, $src", IIC_LdStStore, 1731 [(store i32:$rS, iaddr:$src)]>; 1732 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 1733 "stfs $rS, $dst", IIC_LdStSTFD, 1734 [(store f32:$rS, iaddr:$dst)]>; 1735 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 1736 "stfd $rS, $dst", IIC_LdStSTFD, 1737 [(store f64:$rS, iaddr:$dst)]>; 1738 } 1739 1740 // Unindexed (r+i) Stores with Update (preinc). 1741 let PPC970_Unit = 2, mayStore = 1 in { 1742 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1743 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1744 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1745 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1746 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1747 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1748 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1749 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1750 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1751 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 1752 "stfsu $rS, $dst", IIC_LdStSTFDU, []>, 1753 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1754 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 1755 "stfdu $rS, $dst", IIC_LdStSTFDU, []>, 1756 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1757 } 1758 1759 // Patterns to match the pre-inc stores. We can't put the patterns on 1760 // the instruction definitions directly as ISel wants the address base 1761 // and offset to be separate operands, not a single complex operand. 1762 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1763 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 1764 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1765 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 1766 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1767 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 1768 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1769 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 1770 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1771 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 1772 1773 // Indexed (r+r) Stores. 1774 let PPC970_Unit = 2 in { 1775 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 1776 "stbx $rS, $dst", IIC_LdStStore, 1777 [(truncstorei8 i32:$rS, xaddr:$dst)]>, 1778 PPC970_DGroup_Cracked; 1779 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 1780 "sthx $rS, $dst", IIC_LdStStore, 1781 [(truncstorei16 i32:$rS, xaddr:$dst)]>, 1782 PPC970_DGroup_Cracked; 1783 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 1784 "stwx $rS, $dst", IIC_LdStStore, 1785 [(store i32:$rS, xaddr:$dst)]>, 1786 PPC970_DGroup_Cracked; 1787 1788 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 1789 "sthbrx $rS, $dst", IIC_LdStStore, 1790 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>, 1791 PPC970_DGroup_Cracked; 1792 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 1793 "stwbrx $rS, $dst", IIC_LdStStore, 1794 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>, 1795 PPC970_DGroup_Cracked; 1796 1797 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 1798 "stfiwx $frS, $dst", IIC_LdStSTFD, 1799 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>; 1800 1801 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 1802 "stfsx $frS, $dst", IIC_LdStSTFD, 1803 [(store f32:$frS, xaddr:$dst)]>; 1804 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 1805 "stfdx $frS, $dst", IIC_LdStSTFD, 1806 [(store f64:$frS, xaddr:$dst)]>; 1807 } 1808 1809 // Indexed (r+r) Stores with Update (preinc). 1810 let PPC970_Unit = 2, mayStore = 1 in { 1811 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1812 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1813 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1814 PPC970_DGroup_Cracked; 1815 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1816 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1817 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1818 PPC970_DGroup_Cracked; 1819 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1820 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1821 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1822 PPC970_DGroup_Cracked; 1823 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst), 1824 "stfsux $rS, $dst", IIC_LdStSTFDU, []>, 1825 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1826 PPC970_DGroup_Cracked; 1827 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst), 1828 "stfdux $rS, $dst", IIC_LdStSTFDU, []>, 1829 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1830 PPC970_DGroup_Cracked; 1831 } 1832 1833 // Patterns to match the pre-inc stores. We can't put the patterns on 1834 // the instruction definitions directly as ISel wants the address base 1835 // and offset to be separate operands, not a single complex operand. 1836 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1837 (STBUX $rS, $ptrreg, $ptroff)>; 1838 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1839 (STHUX $rS, $ptrreg, $ptroff)>; 1840 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1841 (STWUX $rS, $ptrreg, $ptroff)>; 1842 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1843 (STFSUX $rS, $ptrreg, $ptroff)>; 1844 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1845 (STFDUX $rS, $ptrreg, $ptroff)>; 1846 1847 // Store Multiple 1848 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 1849 "stmw $rS, $dst", IIC_LdStLMW, []>; 1850 1851 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L), 1852 "sync $L", IIC_LdStSync, []>; 1853 1854 let isCodeGenOnly = 1 in { 1855 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 1856 "msync", IIC_LdStSync, []> { 1857 let L = 0; 1858 } 1859 } 1860 1861 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 1862 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 1863 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 1864 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 1865 1866 //===----------------------------------------------------------------------===// 1867 // PPC32 Arithmetic Instructions. 1868 // 1869 1870 let PPC970_Unit = 1 in { // FXU Operations. 1871 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 1872 "addi $rD, $rA, $imm", IIC_IntSimple, 1873 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 1874 let BaseName = "addic" in { 1875 let Defs = [CARRY] in 1876 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1877 "addic $rD, $rA, $imm", IIC_IntGeneral, 1878 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 1879 RecFormRel, PPC970_DGroup_Cracked; 1880 let Defs = [CARRY, CR0] in 1881 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1882 "addic. $rD, $rA, $imm", IIC_IntGeneral, 1883 []>, isDOT, RecFormRel; 1884 } 1885 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 1886 "addis $rD, $rA, $imm", IIC_IntSimple, 1887 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 1888 let isCodeGenOnly = 1 in 1889 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 1890 "la $rD, $sym($rA)", IIC_IntGeneral, 1891 [(set i32:$rD, (add i32:$rA, 1892 (PPClo tglobaladdr:$sym, 0)))]>; 1893 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1894 "mulli $rD, $rA, $imm", IIC_IntMulLI, 1895 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 1896 let Defs = [CARRY] in 1897 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1898 "subfic $rD, $rA, $imm", IIC_IntGeneral, 1899 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 1900 1901 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 1902 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 1903 "li $rD, $imm", IIC_IntSimple, 1904 [(set i32:$rD, imm32SExt16:$imm)]>; 1905 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 1906 "lis $rD, $imm", IIC_IntSimple, 1907 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 1908 } 1909 } 1910 1911 let PPC970_Unit = 1 in { // FXU Operations. 1912 let Defs = [CR0] in { 1913 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1914 "andi. $dst, $src1, $src2", IIC_IntGeneral, 1915 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 1916 isDOT; 1917 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1918 "andis. $dst, $src1, $src2", IIC_IntGeneral, 1919 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 1920 isDOT; 1921 } 1922 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1923 "ori $dst, $src1, $src2", IIC_IntSimple, 1924 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 1925 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1926 "oris $dst, $src1, $src2", IIC_IntSimple, 1927 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 1928 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1929 "xori $dst, $src1, $src2", IIC_IntSimple, 1930 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 1931 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1932 "xoris $dst, $src1, $src2", IIC_IntSimple, 1933 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 1934 1935 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 1936 []>; 1937 let isCodeGenOnly = 1 in { 1938 // The POWER6 and POWER7 have special group-terminating nops. 1939 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 1940 "ori 1, 1, 0", IIC_IntSimple, []>; 1941 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 1942 "ori 2, 2, 0", IIC_IntSimple, []>; 1943 } 1944 1945 let isCompare = 1, hasSideEffects = 0 in { 1946 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 1947 "cmpwi $crD, $rA, $imm", IIC_IntCompare>; 1948 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 1949 "cmplwi $dst, $src1, $src2", IIC_IntCompare>; 1950 } 1951 } 1952 1953 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 1954 let isCommutable = 1 in { 1955 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1956 "nand", "$rA, $rS, $rB", IIC_IntSimple, 1957 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 1958 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1959 "and", "$rA, $rS, $rB", IIC_IntSimple, 1960 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 1961 } // isCommutable 1962 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1963 "andc", "$rA, $rS, $rB", IIC_IntSimple, 1964 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 1965 let isCommutable = 1 in { 1966 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1967 "or", "$rA, $rS, $rB", IIC_IntSimple, 1968 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 1969 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1970 "nor", "$rA, $rS, $rB", IIC_IntSimple, 1971 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 1972 } // isCommutable 1973 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1974 "orc", "$rA, $rS, $rB", IIC_IntSimple, 1975 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 1976 let isCommutable = 1 in { 1977 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1978 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 1979 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 1980 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1981 "xor", "$rA, $rS, $rB", IIC_IntSimple, 1982 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 1983 } // isCommutable 1984 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1985 "slw", "$rA, $rS, $rB", IIC_IntGeneral, 1986 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 1987 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1988 "srw", "$rA, $rS, $rB", IIC_IntGeneral, 1989 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 1990 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1991 "sraw", "$rA, $rS, $rB", IIC_IntShift, 1992 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 1993 } 1994 1995 let PPC970_Unit = 1 in { // FXU Operations. 1996 let hasSideEffects = 0 in { 1997 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 1998 "srawi", "$rA, $rS, $SH", IIC_IntShift, 1999 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 2000 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 2001 "cntlzw", "$rA, $rS", IIC_IntGeneral, 2002 [(set i32:$rA, (ctlz i32:$rS))]>; 2003 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 2004 "extsb", "$rA, $rS", IIC_IntSimple, 2005 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 2006 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 2007 "extsh", "$rA, $rS", IIC_IntSimple, 2008 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 2009 2010 let isCommutable = 1 in 2011 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2012 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 2013 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>; 2014 } 2015 let isCompare = 1, hasSideEffects = 0 in { 2016 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2017 "cmpw $crD, $rA, $rB", IIC_IntCompare>; 2018 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2019 "cmplw $crD, $rA, $rB", IIC_IntCompare>; 2020 } 2021 } 2022 let PPC970_Unit = 3 in { // FPU Operations. 2023 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 2024 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2025 let isCompare = 1, hasSideEffects = 0 in { 2026 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2027 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2028 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2029 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2030 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2031 } 2032 2033 let Uses = [RM] in { 2034 let hasSideEffects = 0 in { 2035 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), 2036 "fctiw", "$frD, $frB", IIC_FPGeneral, 2037 []>; 2038 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 2039 "fctiwz", "$frD, $frB", IIC_FPGeneral, 2040 [(set f64:$frD, (PPCfctiwz f64:$frB))]>; 2041 2042 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 2043 "frsp", "$frD, $frB", IIC_FPGeneral, 2044 [(set f32:$frD, (fround f64:$frB))]>; 2045 2046 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2047 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 2048 "frin", "$frD, $frB", IIC_FPGeneral, 2049 [(set f64:$frD, (frnd f64:$frB))]>; 2050 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 2051 "frin", "$frD, $frB", IIC_FPGeneral, 2052 [(set f32:$frD, (frnd f32:$frB))]>; 2053 } 2054 2055 let hasSideEffects = 0 in { 2056 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2057 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 2058 "frip", "$frD, $frB", IIC_FPGeneral, 2059 [(set f64:$frD, (fceil f64:$frB))]>; 2060 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 2061 "frip", "$frD, $frB", IIC_FPGeneral, 2062 [(set f32:$frD, (fceil f32:$frB))]>; 2063 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2064 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 2065 "friz", "$frD, $frB", IIC_FPGeneral, 2066 [(set f64:$frD, (ftrunc f64:$frB))]>; 2067 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 2068 "friz", "$frD, $frB", IIC_FPGeneral, 2069 [(set f32:$frD, (ftrunc f32:$frB))]>; 2070 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2071 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 2072 "frim", "$frD, $frB", IIC_FPGeneral, 2073 [(set f64:$frD, (ffloor f64:$frB))]>; 2074 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 2075 "frim", "$frD, $frB", IIC_FPGeneral, 2076 [(set f32:$frD, (ffloor f32:$frB))]>; 2077 2078 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 2079 "fsqrt", "$frD, $frB", IIC_FPSqrtD, 2080 [(set f64:$frD, (fsqrt f64:$frB))]>; 2081 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 2082 "fsqrts", "$frD, $frB", IIC_FPSqrtS, 2083 [(set f32:$frD, (fsqrt f32:$frB))]>; 2084 } 2085 } 2086 } 2087 2088 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2089 /// often coalesced away and we don't want the dispatch group builder to think 2090 /// that they will fill slots (which could cause the load of a LSU reject to 2091 /// sneak into a d-group with a store). 2092 let hasSideEffects = 0 in 2093 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 2094 "fmr", "$frD, $frB", IIC_FPGeneral, 2095 []>, // (set f32:$frD, f32:$frB) 2096 PPC970_Unit_Pseudo; 2097 2098 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations. 2099 // These are artificially split into two different forms, for 4/8 byte FP. 2100 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 2101 "fabs", "$frD, $frB", IIC_FPGeneral, 2102 [(set f32:$frD, (fabs f32:$frB))]>; 2103 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2104 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 2105 "fabs", "$frD, $frB", IIC_FPGeneral, 2106 [(set f64:$frD, (fabs f64:$frB))]>; 2107 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 2108 "fnabs", "$frD, $frB", IIC_FPGeneral, 2109 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 2110 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2111 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 2112 "fnabs", "$frD, $frB", IIC_FPGeneral, 2113 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 2114 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 2115 "fneg", "$frD, $frB", IIC_FPGeneral, 2116 [(set f32:$frD, (fneg f32:$frB))]>; 2117 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2118 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 2119 "fneg", "$frD, $frB", IIC_FPGeneral, 2120 [(set f64:$frD, (fneg f64:$frB))]>; 2121 2122 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), 2123 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2124 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; 2125 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2126 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), 2127 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2128 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; 2129 2130 // Reciprocal estimates. 2131 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 2132 "fre", "$frD, $frB", IIC_FPGeneral, 2133 [(set f64:$frD, (PPCfre f64:$frB))]>; 2134 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 2135 "fres", "$frD, $frB", IIC_FPGeneral, 2136 [(set f32:$frD, (PPCfre f32:$frB))]>; 2137 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 2138 "frsqrte", "$frD, $frB", IIC_FPGeneral, 2139 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 2140 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 2141 "frsqrtes", "$frD, $frB", IIC_FPGeneral, 2142 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 2143 } 2144 2145 // XL-Form instructions. condition register logical ops. 2146 // 2147 let hasSideEffects = 0 in 2148 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2149 "mcrf $BF, $BFA", IIC_BrMCR>, 2150 PPC970_DGroup_First, PPC970_Unit_CRU; 2151 2152 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2153 // condition-register logical instructions have preferred forms. Specifically, 2154 // it is preferred that the bit specified by the BT field be in the same 2155 // condition register as that specified by the bit BB. We might want to account 2156 // for this via hinting the register allocator and anti-dep breakers, or we 2157 // could constrain the register class to force this constraint and then loosen 2158 // it during register allocation via convertToThreeAddress or some similar 2159 // mechanism. 2160 2161 let isCommutable = 1 in { 2162 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2163 (ins crbitrc:$CRA, crbitrc:$CRB), 2164 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2165 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2166 2167 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2168 (ins crbitrc:$CRA, crbitrc:$CRB), 2169 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2170 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2171 2172 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2173 (ins crbitrc:$CRA, crbitrc:$CRB), 2174 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2175 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2176 2177 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2178 (ins crbitrc:$CRA, crbitrc:$CRB), 2179 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2180 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2181 2182 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2183 (ins crbitrc:$CRA, crbitrc:$CRB), 2184 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2185 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2186 2187 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2188 (ins crbitrc:$CRA, crbitrc:$CRB), 2189 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2190 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2191 } // isCommutable 2192 2193 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2194 (ins crbitrc:$CRA, crbitrc:$CRB), 2195 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2196 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2197 2198 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2199 (ins crbitrc:$CRA, crbitrc:$CRB), 2200 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2201 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2202 2203 let isCodeGenOnly = 1 in { 2204 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 2205 "creqv $dst, $dst, $dst", IIC_BrCR, 2206 [(set i1:$dst, 1)]>; 2207 2208 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 2209 "crxor $dst, $dst, $dst", IIC_BrCR, 2210 [(set i1:$dst, 0)]>; 2211 2212 let Defs = [CR1EQ], CRD = 6 in { 2213 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2214 "creqv 6, 6, 6", IIC_BrCR, 2215 [(PPCcr6set)]>; 2216 2217 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2218 "crxor 6, 6, 6", IIC_BrCR, 2219 [(PPCcr6unset)]>; 2220 } 2221 } 2222 2223 // XFX-Form instructions. Instructions that deal with SPRs. 2224 // 2225 2226 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 2227 "mfspr $RT, $SPR", IIC_SprMFSPR>; 2228 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 2229 "mtspr $SPR, $RT", IIC_SprMTSPR>; 2230 2231 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 2232 "mftb $RT, $SPR", IIC_SprMFTB>; 2233 2234 // A pseudo-instruction used to implement the read of the 64-bit cycle counter 2235 // on a 32-bit target. 2236 let hasSideEffects = 1, usesCustomInserter = 1 in 2237 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins), 2238 "#ReadTB", []>; 2239 2240 let Uses = [CTR] in { 2241 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 2242 "mfctr $rT", IIC_SprMFSPR>, 2243 PPC970_DGroup_First, PPC970_Unit_FXU; 2244 } 2245 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 2246 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2247 "mtctr $rS", IIC_SprMTSPR>, 2248 PPC970_DGroup_First, PPC970_Unit_FXU; 2249 } 2250 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 2251 let Pattern = [(int_ppc_mtctr i32:$rS)] in 2252 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2253 "mtctr $rS", IIC_SprMTSPR>, 2254 PPC970_DGroup_First, PPC970_Unit_FXU; 2255 } 2256 2257 let Defs = [LR] in { 2258 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 2259 "mtlr $rS", IIC_SprMTSPR>, 2260 PPC970_DGroup_First, PPC970_Unit_FXU; 2261 } 2262 let Uses = [LR] in { 2263 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 2264 "mflr $rT", IIC_SprMFSPR>, 2265 PPC970_DGroup_First, PPC970_Unit_FXU; 2266 } 2267 2268 let isCodeGenOnly = 1 in { 2269 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2270 // like a GPR on the PPC970. As such, copies in and out have the same 2271 // performance characteristics as an OR instruction. 2272 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 2273 "mtspr 256, $rS", IIC_IntGeneral>, 2274 PPC970_DGroup_Single, PPC970_Unit_FXU; 2275 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 2276 "mfspr $rT, 256", IIC_IntGeneral>, 2277 PPC970_DGroup_First, PPC970_Unit_FXU; 2278 2279 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 2280 (outs VRSAVERC:$reg), (ins gprc:$rS), 2281 "mtspr 256, $rS", IIC_IntGeneral>, 2282 PPC970_DGroup_Single, PPC970_Unit_FXU; 2283 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 2284 (ins VRSAVERC:$reg), 2285 "mfspr $rT, 256", IIC_IntGeneral>, 2286 PPC970_DGroup_First, PPC970_Unit_FXU; 2287 } 2288 2289 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register, 2290 // so we'll need to scavenge a register for it. 2291 let mayStore = 1 in 2292 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F), 2293 "#SPILL_VRSAVE", []>; 2294 2295 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously 2296 // spilled), so we'll need to scavenge a register for it. 2297 let mayLoad = 1 in 2298 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), 2299 "#RESTORE_VRSAVE", []>; 2300 2301 let hasSideEffects = 0 in { 2302 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 2303 "mtocrf $FXM, $ST", IIC_BrMCRX>, 2304 PPC970_DGroup_First, PPC970_Unit_CRU; 2305 2306 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 2307 "mtcrf $FXM, $rS", IIC_BrMCRX>, 2308 PPC970_MicroCode, PPC970_Unit_CRU; 2309 2310 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. 2311 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 2312 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 2313 PPC970_DGroup_First, PPC970_Unit_CRU; 2314 2315 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 2316 "mfcr $rT", IIC_SprMFCR>, 2317 PPC970_MicroCode, PPC970_Unit_CRU; 2318 } // hasSideEffects = 0 2319 2320 // Pseudo instruction to perform FADD in round-to-zero mode. 2321 let usesCustomInserter = 1, Uses = [RM] in { 2322 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2323 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>; 2324 } 2325 2326 // The above pseudo gets expanded to make use of the following instructions 2327 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2328 let Uses = [RM], Defs = [RM] in { 2329 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2330 "mtfsb0 $FM", IIC_IntMTFSB0, []>, 2331 PPC970_DGroup_Single, PPC970_Unit_FPU; 2332 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2333 "mtfsb1 $FM", IIC_IntMTFSB0, []>, 2334 PPC970_DGroup_Single, PPC970_Unit_FPU; 2335 let isCodeGenOnly = 1 in 2336 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 2337 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>, 2338 PPC970_DGroup_Single, PPC970_Unit_FPU; 2339 } 2340 let Uses = [RM] in { 2341 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2342 "mffs $rT", IIC_IntMFFS, 2343 [(set f64:$rT, (PPCmffs))]>, 2344 PPC970_DGroup_Single, PPC970_Unit_FPU; 2345 2346 let Defs = [CR1] in 2347 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2348 "mffs. $rT", IIC_IntMFFS, []>, isDOT; 2349 } 2350 2351 2352 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2353 // XO-Form instructions. Arithmetic instructions that can set overflow bit 2354 let isCommutable = 1 in 2355 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2356 "add", "$rT, $rA, $rB", IIC_IntSimple, 2357 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 2358 let isCodeGenOnly = 1 in 2359 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), 2360 "add $rT, $rA, $rB", IIC_IntSimple, 2361 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; 2362 let isCommutable = 1 in 2363 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2364 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 2365 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 2366 PPC970_DGroup_Cracked; 2367 2368 defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2369 "divw", "$rT, $rA, $rB", IIC_IntDivW, 2370 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>; 2371 defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2372 "divwu", "$rT, $rA, $rB", IIC_IntDivW, 2373 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>; 2374 def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2375 "divwe $rT, $rA, $rB", IIC_IntDivW, 2376 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>, 2377 Requires<[HasExtDiv]>; 2378 let Defs = [CR0] in 2379 def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2380 "divwe. $rT, $rA, $rB", IIC_IntDivW, 2381 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 2382 Requires<[HasExtDiv]>; 2383 def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2384 "divweu $rT, $rA, $rB", IIC_IntDivW, 2385 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>, 2386 Requires<[HasExtDiv]>; 2387 let Defs = [CR0] in 2388 def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2389 "divweu. $rT, $rA, $rB", IIC_IntDivW, 2390 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 2391 Requires<[HasExtDiv]>; 2392 let isCommutable = 1 in { 2393 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2394 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, 2395 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 2396 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2397 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, 2398 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 2399 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2400 "mullw", "$rT, $rA, $rB", IIC_IntMulHW, 2401 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 2402 } // isCommutable 2403 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2404 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 2405 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 2406 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2407 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 2408 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 2409 PPC970_DGroup_Cracked; 2410 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 2411 "neg", "$rT, $rA", IIC_IntSimple, 2412 [(set i32:$rT, (ineg i32:$rA))]>; 2413 let Uses = [CARRY] in { 2414 let isCommutable = 1 in 2415 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2416 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 2417 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 2418 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 2419 "addme", "$rT, $rA", IIC_IntGeneral, 2420 [(set i32:$rT, (adde i32:$rA, -1))]>; 2421 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 2422 "addze", "$rT, $rA", IIC_IntGeneral, 2423 [(set i32:$rT, (adde i32:$rA, 0))]>; 2424 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2425 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 2426 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 2427 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 2428 "subfme", "$rT, $rA", IIC_IntGeneral, 2429 [(set i32:$rT, (sube -1, i32:$rA))]>; 2430 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 2431 "subfze", "$rT, $rA", IIC_IntGeneral, 2432 [(set i32:$rT, (sube 0, i32:$rA))]>; 2433 } 2434 } 2435 2436 // A-Form instructions. Most of the instructions executed in the FPU are of 2437 // this type. 2438 // 2439 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations. 2440 let Uses = [RM] in { 2441 let isCommutable = 1 in { 2442 defm FMADD : AForm_1r<63, 29, 2443 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2444 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2445 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2446 defm FMADDS : AForm_1r<59, 29, 2447 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2448 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2449 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2450 defm FMSUB : AForm_1r<63, 28, 2451 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2452 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2453 [(set f64:$FRT, 2454 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2455 defm FMSUBS : AForm_1r<59, 28, 2456 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2457 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2458 [(set f32:$FRT, 2459 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 2460 defm FNMADD : AForm_1r<63, 31, 2461 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2462 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2463 [(set f64:$FRT, 2464 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 2465 defm FNMADDS : AForm_1r<59, 31, 2466 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2467 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2468 [(set f32:$FRT, 2469 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 2470 defm FNMSUB : AForm_1r<63, 30, 2471 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2472 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2473 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC, 2474 (fneg f64:$FRB))))]>; 2475 defm FNMSUBS : AForm_1r<59, 30, 2476 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2477 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2478 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC, 2479 (fneg f32:$FRB))))]>; 2480 } // isCommutable 2481 } 2482 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 2483 // having 4 of these, force the comparison to always be an 8-byte double (code 2484 // should use an FMRSD if the input comparison value really wants to be a float) 2485 // and 4/8 byte forms for the result and operand type.. 2486 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2487 defm FSELD : AForm_1r<63, 23, 2488 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2489 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2490 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 2491 defm FSELS : AForm_1r<63, 23, 2492 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2493 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2494 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 2495 let Uses = [RM] in { 2496 let isCommutable = 1 in { 2497 defm FADD : AForm_2r<63, 21, 2498 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2499 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2500 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>; 2501 defm FADDS : AForm_2r<59, 21, 2502 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2503 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2504 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>; 2505 } // isCommutable 2506 defm FDIV : AForm_2r<63, 18, 2507 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2508 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 2509 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>; 2510 defm FDIVS : AForm_2r<59, 18, 2511 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2512 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 2513 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>; 2514 let isCommutable = 1 in { 2515 defm FMUL : AForm_3r<63, 25, 2516 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 2517 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 2518 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>; 2519 defm FMULS : AForm_3r<59, 25, 2520 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 2521 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 2522 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>; 2523 } // isCommutable 2524 defm FSUB : AForm_2r<63, 20, 2525 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2526 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2527 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>; 2528 defm FSUBS : AForm_2r<59, 20, 2529 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2530 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2531 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>; 2532 } 2533 } 2534 2535 let hasSideEffects = 0 in { 2536 let PPC970_Unit = 1 in { // FXU Operations. 2537 let isSelect = 1 in 2538 def ISEL : AForm_4<31, 15, 2539 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 2540 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 2541 []>; 2542 } 2543 2544 let PPC970_Unit = 1 in { // FXU Operations. 2545 // M-Form instructions. rotate and mask instructions. 2546 // 2547 let isCommutable = 1 in { 2548 // RLWIMI can be commuted if the rotate amount is zero. 2549 defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 2550 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 2551 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 2552 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 2553 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 2554 } 2555 let BaseName = "rlwinm" in { 2556 def RLWINM : MForm_2<21, 2557 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2558 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2559 []>, RecFormRel; 2560 let Defs = [CR0] in 2561 def RLWINMo : MForm_2<21, 2562 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2563 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2564 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked; 2565 } 2566 defm RLWNM : MForm_2r<23, (outs gprc:$rA), 2567 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 2568 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 2569 []>; 2570 } 2571 } // hasSideEffects = 0 2572 2573 //===----------------------------------------------------------------------===// 2574 // PowerPC Instruction Patterns 2575 // 2576 2577 // Arbitrary immediate support. Implement in terms of LIS/ORI. 2578 def : Pat<(i32 imm:$imm), 2579 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 2580 2581 // Implement the 'not' operation with the NOR instruction. 2582 def i32not : OutPatFrag<(ops node:$in), 2583 (NOR $in, $in)>; 2584 def : Pat<(not i32:$in), 2585 (i32not $in)>; 2586 2587 // ADD an arbitrary immediate. 2588 def : Pat<(add i32:$in, imm:$imm), 2589 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 2590 // OR an arbitrary immediate. 2591 def : Pat<(or i32:$in, imm:$imm), 2592 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2593 // XOR an arbitrary immediate. 2594 def : Pat<(xor i32:$in, imm:$imm), 2595 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2596 // SUBFIC 2597 def : Pat<(sub imm32SExt16:$imm, i32:$in), 2598 (SUBFIC $in, imm:$imm)>; 2599 2600 // SHL/SRL 2601 def : Pat<(shl i32:$in, (i32 imm:$imm)), 2602 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 2603 def : Pat<(srl i32:$in, (i32 imm:$imm)), 2604 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 2605 2606 // ROTL 2607 def : Pat<(rotl i32:$in, i32:$sh), 2608 (RLWNM $in, $sh, 0, 31)>; 2609 def : Pat<(rotl i32:$in, (i32 imm:$imm)), 2610 (RLWINM $in, imm:$imm, 0, 31)>; 2611 2612 // RLWNM 2613 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 2614 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 2615 2616 // Calls 2617 def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 2618 (BL tglobaladdr:$dst)>; 2619 def : Pat<(PPCcall (i32 texternalsym:$dst)), 2620 (BL texternalsym:$dst)>; 2621 2622 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 2623 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 2624 2625 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 2626 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 2627 2628 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 2629 (TCRETURNri CTRRC:$dst, imm:$imm)>; 2630 2631 2632 2633 // Hi and Lo for Darwin Global Addresses. 2634 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 2635 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 2636 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 2637 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 2638 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 2639 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 2640 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 2641 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 2642 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 2643 (ADDIS $in, tglobaltlsaddr:$g)>; 2644 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 2645 (ADDI $in, tglobaltlsaddr:$g)>; 2646 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 2647 (ADDIS $in, tglobaladdr:$g)>; 2648 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 2649 (ADDIS $in, tconstpool:$g)>; 2650 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 2651 (ADDIS $in, tjumptable:$g)>; 2652 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 2653 (ADDIS $in, tblockaddress:$g)>; 2654 2655 // Support for thread-local storage. 2656 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 2657 [(set i32:$rD, (PPCppc32GOT))]>; 2658 2659 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 2660 // This uses two output registers, the first as the real output, the second as a 2661 // temporary register, used internally in code generation. 2662 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 2663 []>, NoEncode<"$rT">; 2664 2665 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 2666 "#LDgotTprelL32", 2667 [(set i32:$rD, 2668 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 2669 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 2670 (ADD4TLS $in, tglobaltlsaddr:$g)>; 2671 2672 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 2673 "#ADDItlsgdL32", 2674 [(set i32:$rD, 2675 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 2676 // LR is a true define, while the rest of the Defs are clobbers. R3 is 2677 // explicitly defined when this op is created, so not mentioned here. 2678 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 2679 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 2680 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 2681 "GETtlsADDR32", 2682 [(set i32:$rD, 2683 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 2684 // Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 2685 // are true defines while the rest of the Defs are clobbers. 2686 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 2687 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 2688 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD), 2689 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 2690 "#ADDItlsgdLADDR32", 2691 [(set i32:$rD, 2692 (PPCaddiTlsgdLAddr i32:$reg, 2693 tglobaltlsaddr:$disp, 2694 tglobaltlsaddr:$sym))]>; 2695 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 2696 "#ADDItlsldL32", 2697 [(set i32:$rD, 2698 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 2699 // LR is a true define, while the rest of the Defs are clobbers. R3 is 2700 // explicitly defined when this op is created, so not mentioned here. 2701 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 2702 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 2703 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 2704 "GETtlsldADDR32", 2705 [(set i32:$rD, 2706 (PPCgetTlsldAddr i32:$reg, 2707 tglobaltlsaddr:$sym))]>; 2708 // Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 2709 // are true defines while the rest of the Defs are clobbers. 2710 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 2711 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 2712 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD), 2713 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 2714 "#ADDItlsldLADDR32", 2715 [(set i32:$rD, 2716 (PPCaddiTlsldLAddr i32:$reg, 2717 tglobaltlsaddr:$disp, 2718 tglobaltlsaddr:$sym))]>; 2719 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 2720 "#ADDIdtprelL32", 2721 [(set i32:$rD, 2722 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 2723 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 2724 "#ADDISdtprelHA32", 2725 [(set i32:$rD, 2726 (PPCaddisDtprelHA i32:$reg, 2727 tglobaltlsaddr:$disp))]>; 2728 2729 // Support for Position-independent code 2730 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 2731 "#LWZtoc", 2732 [(set i32:$rD, 2733 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 2734 // Get Global (GOT) Base Register offset, from the word immediately preceding 2735 // the function label. 2736 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 2737 2738 2739 // Standard shifts. These are represented separately from the real shifts above 2740 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift 2741 // amounts. 2742 def : Pat<(sra i32:$rS, i32:$rB), 2743 (SRAW $rS, $rB)>; 2744 def : Pat<(srl i32:$rS, i32:$rB), 2745 (SRW $rS, $rB)>; 2746 def : Pat<(shl i32:$rS, i32:$rB), 2747 (SLW $rS, $rB)>; 2748 2749 def : Pat<(zextloadi1 iaddr:$src), 2750 (LBZ iaddr:$src)>; 2751 def : Pat<(zextloadi1 xaddr:$src), 2752 (LBZX xaddr:$src)>; 2753 def : Pat<(extloadi1 iaddr:$src), 2754 (LBZ iaddr:$src)>; 2755 def : Pat<(extloadi1 xaddr:$src), 2756 (LBZX xaddr:$src)>; 2757 def : Pat<(extloadi8 iaddr:$src), 2758 (LBZ iaddr:$src)>; 2759 def : Pat<(extloadi8 xaddr:$src), 2760 (LBZX xaddr:$src)>; 2761 def : Pat<(extloadi16 iaddr:$src), 2762 (LHZ iaddr:$src)>; 2763 def : Pat<(extloadi16 xaddr:$src), 2764 (LHZX xaddr:$src)>; 2765 def : Pat<(f64 (extloadf32 iaddr:$src)), 2766 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 2767 def : Pat<(f64 (extloadf32 xaddr:$src)), 2768 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 2769 2770 def : Pat<(f64 (fextend f32:$src)), 2771 (COPY_TO_REGCLASS $src, F8RC)>; 2772 2773 // Only seq_cst fences require the heavyweight sync (SYNC 0). 2774 // All others can use the lightweight sync (SYNC 1). 2775 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 2776 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 2777 // versions of Power. 2778 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>; 2779 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>; 2780 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>; 2781 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2782 2783 // Additional FNMSUB patterns: -a*c + b == -(a*c - b) 2784 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), 2785 (FNMSUB $A, $C, $B)>; 2786 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B), 2787 (FNMSUB $A, $C, $B)>; 2788 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B), 2789 (FNMSUBS $A, $C, $B)>; 2790 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B), 2791 (FNMSUBS $A, $C, $B)>; 2792 2793 // FCOPYSIGN's operand types need not agree. 2794 def : Pat<(fcopysign f64:$frB, f32:$frA), 2795 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 2796 def : Pat<(fcopysign f32:$frB, f64:$frA), 2797 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 2798 2799 include "PPCInstrAltivec.td" 2800 include "PPCInstrSPE.td" 2801 include "PPCInstr64Bit.td" 2802 include "PPCInstrVSX.td" 2803 include "PPCInstrQPX.td" 2804 include "PPCInstrHTM.td" 2805 2806 def crnot : OutPatFrag<(ops node:$in), 2807 (CRNOR $in, $in)>; 2808 def : Pat<(not i1:$in), 2809 (crnot $in)>; 2810 2811 // Patterns for arithmetic i1 operations. 2812 def : Pat<(add i1:$a, i1:$b), 2813 (CRXOR $a, $b)>; 2814 def : Pat<(sub i1:$a, i1:$b), 2815 (CRXOR $a, $b)>; 2816 def : Pat<(mul i1:$a, i1:$b), 2817 (CRAND $a, $b)>; 2818 2819 // We're sometimes asked to materialize i1 -1, which is just 1 in this case 2820 // (-1 is used to mean all bits set). 2821 def : Pat<(i1 -1), (CRSET)>; 2822 2823 // i1 extensions, implemented in terms of isel. 2824 def : Pat<(i32 (zext i1:$in)), 2825 (SELECT_I4 $in, (LI 1), (LI 0))>; 2826 def : Pat<(i32 (sext i1:$in)), 2827 (SELECT_I4 $in, (LI -1), (LI 0))>; 2828 2829 def : Pat<(i64 (zext i1:$in)), 2830 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 2831 def : Pat<(i64 (sext i1:$in)), 2832 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 2833 2834 // FIXME: We should choose either a zext or a sext based on other constants 2835 // already around. 2836 def : Pat<(i32 (anyext i1:$in)), 2837 (SELECT_I4 $in, (LI 1), (LI 0))>; 2838 def : Pat<(i64 (anyext i1:$in)), 2839 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 2840 2841 // match setcc on i1 variables. 2842 // CRANDC is: 2843 // 1 1 : F 2844 // 1 0 : T 2845 // 0 1 : F 2846 // 0 0 : F 2847 // 2848 // LT is: 2849 // -1 -1 : F 2850 // -1 0 : T 2851 // 0 -1 : F 2852 // 0 0 : F 2853 // 2854 // ULT is: 2855 // 1 1 : F 2856 // 1 0 : F 2857 // 0 1 : T 2858 // 0 0 : F 2859 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 2860 (CRANDC $s1, $s2)>; 2861 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 2862 (CRANDC $s2, $s1)>; 2863 // CRORC is: 2864 // 1 1 : T 2865 // 1 0 : T 2866 // 0 1 : F 2867 // 0 0 : T 2868 // 2869 // LE is: 2870 // -1 -1 : T 2871 // -1 0 : T 2872 // 0 -1 : F 2873 // 0 0 : T 2874 // 2875 // ULE is: 2876 // 1 1 : T 2877 // 1 0 : F 2878 // 0 1 : T 2879 // 0 0 : T 2880 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 2881 (CRORC $s1, $s2)>; 2882 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 2883 (CRORC $s2, $s1)>; 2884 2885 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 2886 (CREQV $s1, $s2)>; 2887 2888 // GE is: 2889 // -1 -1 : T 2890 // -1 0 : F 2891 // 0 -1 : T 2892 // 0 0 : T 2893 // 2894 // UGE is: 2895 // 1 1 : T 2896 // 1 0 : T 2897 // 0 1 : F 2898 // 0 0 : T 2899 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 2900 (CRORC $s2, $s1)>; 2901 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 2902 (CRORC $s1, $s2)>; 2903 2904 // GT is: 2905 // -1 -1 : F 2906 // -1 0 : F 2907 // 0 -1 : T 2908 // 0 0 : F 2909 // 2910 // UGT is: 2911 // 1 1 : F 2912 // 1 0 : T 2913 // 0 1 : F 2914 // 0 0 : F 2915 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 2916 (CRANDC $s2, $s1)>; 2917 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 2918 (CRANDC $s1, $s2)>; 2919 2920 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 2921 (CRXOR $s1, $s2)>; 2922 2923 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 2924 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 2925 // floating-point types. 2926 2927 multiclass CRNotPat<dag pattern, dag result> { 2928 def : Pat<pattern, (crnot result)>; 2929 def : Pat<(not pattern), result>; 2930 2931 // We can also fold the crnot into an extension: 2932 def : Pat<(i32 (zext pattern)), 2933 (SELECT_I4 result, (LI 0), (LI 1))>; 2934 def : Pat<(i32 (sext pattern)), 2935 (SELECT_I4 result, (LI 0), (LI -1))>; 2936 2937 // We can also fold the crnot into an extension: 2938 def : Pat<(i64 (zext pattern)), 2939 (SELECT_I8 result, (LI8 0), (LI8 1))>; 2940 def : Pat<(i64 (sext pattern)), 2941 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 2942 2943 // FIXME: We should choose either a zext or a sext based on other constants 2944 // already around. 2945 def : Pat<(i32 (anyext pattern)), 2946 (SELECT_I4 result, (LI 0), (LI 1))>; 2947 2948 def : Pat<(i64 (anyext pattern)), 2949 (SELECT_I8 result, (LI8 0), (LI8 1))>; 2950 } 2951 2952 // FIXME: Because of what seems like a bug in TableGen's type-inference code, 2953 // we need to write imm:$imm in the output patterns below, not just $imm, or 2954 // else the resulting matcher will not correctly add the immediate operand 2955 // (making it a register operand instead). 2956 2957 // extended SETCC. 2958 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 2959 OutPatFrag rfrag, OutPatFrag rfrag8> { 2960 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 2961 (rfrag $s1)>; 2962 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 2963 (rfrag8 $s1)>; 2964 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 2965 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 2966 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 2967 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 2968 2969 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 2970 (rfrag $s1)>; 2971 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 2972 (rfrag8 $s1)>; 2973 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 2974 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 2975 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 2976 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 2977 } 2978 2979 // Note that we do all inversions below with i(32|64)not, instead of using 2980 // (xori x, 1) because on the A2 nor has single-cycle latency while xori 2981 // has 2-cycle latency. 2982 2983 defm : ExtSetCCPat<SETEQ, 2984 PatFrag<(ops node:$in, node:$cc), 2985 (setcc $in, 0, $cc)>, 2986 OutPatFrag<(ops node:$in), 2987 (RLWINM (CNTLZW $in), 27, 31, 31)>, 2988 OutPatFrag<(ops node:$in), 2989 (RLDICL (CNTLZD $in), 58, 63)> >; 2990 2991 defm : ExtSetCCPat<SETNE, 2992 PatFrag<(ops node:$in, node:$cc), 2993 (setcc $in, 0, $cc)>, 2994 OutPatFrag<(ops node:$in), 2995 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 2996 OutPatFrag<(ops node:$in), 2997 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 2998 2999 defm : ExtSetCCPat<SETLT, 3000 PatFrag<(ops node:$in, node:$cc), 3001 (setcc $in, 0, $cc)>, 3002 OutPatFrag<(ops node:$in), 3003 (RLWINM $in, 1, 31, 31)>, 3004 OutPatFrag<(ops node:$in), 3005 (RLDICL $in, 1, 63)> >; 3006 3007 defm : ExtSetCCPat<SETGE, 3008 PatFrag<(ops node:$in, node:$cc), 3009 (setcc $in, 0, $cc)>, 3010 OutPatFrag<(ops node:$in), 3011 (RLWINM (i32not $in), 1, 31, 31)>, 3012 OutPatFrag<(ops node:$in), 3013 (RLDICL (i64not $in), 1, 63)> >; 3014 3015 defm : ExtSetCCPat<SETGT, 3016 PatFrag<(ops node:$in, node:$cc), 3017 (setcc $in, 0, $cc)>, 3018 OutPatFrag<(ops node:$in), 3019 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3020 OutPatFrag<(ops node:$in), 3021 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3022 3023 defm : ExtSetCCPat<SETLE, 3024 PatFrag<(ops node:$in, node:$cc), 3025 (setcc $in, 0, $cc)>, 3026 OutPatFrag<(ops node:$in), 3027 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3028 OutPatFrag<(ops node:$in), 3029 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3030 3031 defm : ExtSetCCPat<SETLT, 3032 PatFrag<(ops node:$in, node:$cc), 3033 (setcc $in, -1, $cc)>, 3034 OutPatFrag<(ops node:$in), 3035 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3036 OutPatFrag<(ops node:$in), 3037 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3038 3039 defm : ExtSetCCPat<SETGE, 3040 PatFrag<(ops node:$in, node:$cc), 3041 (setcc $in, -1, $cc)>, 3042 OutPatFrag<(ops node:$in), 3043 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3044 OutPatFrag<(ops node:$in), 3045 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3046 3047 defm : ExtSetCCPat<SETGT, 3048 PatFrag<(ops node:$in, node:$cc), 3049 (setcc $in, -1, $cc)>, 3050 OutPatFrag<(ops node:$in), 3051 (RLWINM (i32not $in), 1, 31, 31)>, 3052 OutPatFrag<(ops node:$in), 3053 (RLDICL (i64not $in), 1, 63)> >; 3054 3055 defm : ExtSetCCPat<SETLE, 3056 PatFrag<(ops node:$in, node:$cc), 3057 (setcc $in, -1, $cc)>, 3058 OutPatFrag<(ops node:$in), 3059 (RLWINM $in, 1, 31, 31)>, 3060 OutPatFrag<(ops node:$in), 3061 (RLDICL $in, 1, 63)> >; 3062 3063 // SETCC for i32. 3064 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3065 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3066 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3067 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3068 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3069 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3070 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3071 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3072 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3073 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3074 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3075 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3076 3077 // For non-equality comparisons, the default code would materialize the 3078 // constant, then compare against it, like this: 3079 // lis r2, 4660 3080 // ori r2, r2, 22136 3081 // cmpw cr0, r3, r2 3082 // beq cr0,L6 3083 // Since we are just comparing for equality, we can emit this instead: 3084 // xoris r0,r3,0x1234 3085 // cmplwi cr0,r0,0x5678 3086 // beq cr0,L6 3087 3088 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3089 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3090 (LO16 imm:$imm)), sub_eq)>; 3091 3092 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3093 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3094 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3095 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3096 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3097 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3098 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3099 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3100 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3101 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3102 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3103 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3104 3105 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3106 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3107 (LO16 imm:$imm)), sub_eq)>; 3108 3109 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3110 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3111 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3112 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3113 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3114 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3115 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3116 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3117 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3118 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3119 3120 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3121 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3122 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3123 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3124 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3125 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3126 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3127 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3128 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3129 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3130 3131 // SETCC for i64. 3132 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3133 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3134 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3135 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3136 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3137 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3138 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3139 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3140 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3141 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3142 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3143 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3144 3145 // For non-equality comparisons, the default code would materialize the 3146 // constant, then compare against it, like this: 3147 // lis r2, 4660 3148 // ori r2, r2, 22136 3149 // cmpd cr0, r3, r2 3150 // beq cr0,L6 3151 // Since we are just comparing for equality, we can emit this instead: 3152 // xoris r0,r3,0x1234 3153 // cmpldi cr0,r0,0x5678 3154 // beq cr0,L6 3155 3156 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3157 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3158 (LO16 imm:$imm)), sub_eq)>; 3159 3160 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3161 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3162 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3163 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3164 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3165 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3166 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3167 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3168 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3169 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3170 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3171 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3172 3173 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3174 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3175 (LO16 imm:$imm)), sub_eq)>; 3176 3177 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3178 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3179 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3180 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3181 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3182 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3183 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3184 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3185 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3186 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3187 3188 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3189 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3190 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3191 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3192 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3193 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3194 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3195 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3196 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3197 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3198 3199 // SETCC for f32. 3200 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)), 3201 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3202 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)), 3203 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3204 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)), 3205 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3206 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)), 3207 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3208 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)), 3209 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3210 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)), 3211 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3212 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)), 3213 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 3214 3215 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)), 3216 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3217 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)), 3218 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3219 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 3220 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3221 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)), 3222 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3223 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)), 3224 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3225 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)), 3226 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3227 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)), 3228 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 3229 3230 // SETCC for f64. 3231 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)), 3232 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3233 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)), 3234 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3235 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)), 3236 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3237 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)), 3238 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3239 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)), 3240 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3241 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)), 3242 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3243 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)), 3244 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 3245 3246 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)), 3247 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3248 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)), 3249 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3250 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), 3251 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3252 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)), 3253 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3254 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)), 3255 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3256 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)), 3257 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3258 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)), 3259 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 3260 3261 // match select on i1 variables: 3262 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 3263 (CROR (CRAND $cond , $tval), 3264 (CRAND (crnot $cond), $fval))>; 3265 3266 // match selectcc on i1 variables: 3267 // select (lhs == rhs), tval, fval is: 3268 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 3269 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 3270 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 3271 (CRAND (CRORC $rhs, $lhs), $fval))>; 3272 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 3273 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 3274 (CRAND (CRORC $lhs, $rhs), $fval))>; 3275 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 3276 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 3277 (CRAND (CRANDC $rhs, $lhs), $fval))>; 3278 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 3279 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 3280 (CRAND (CRANDC $lhs, $rhs), $fval))>; 3281 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 3282 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 3283 (CRAND (CRXOR $lhs, $rhs), $fval))>; 3284 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 3285 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 3286 (CRAND (CRANDC $lhs, $rhs), $fval))>; 3287 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 3288 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 3289 (CRAND (CRANDC $rhs, $lhs), $fval))>; 3290 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 3291 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 3292 (CRAND (CRORC $lhs, $rhs), $fval))>; 3293 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 3294 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 3295 (CRAND (CRORC $rhs, $lhs), $fval))>; 3296 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 3297 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 3298 (CRAND (CRXOR $lhs, $rhs), $tval))>; 3299 3300 // match selectcc on i1 variables with non-i1 output. 3301 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 3302 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3303 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 3304 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3305 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 3306 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 3307 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 3308 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 3309 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 3310 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 3311 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 3312 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 3313 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 3314 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 3315 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 3316 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3317 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 3318 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3319 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 3320 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 3321 3322 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 3323 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3324 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 3325 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3326 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 3327 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 3328 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 3329 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 3330 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 3331 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 3332 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 3333 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 3334 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 3335 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 3336 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 3337 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3338 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 3339 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3340 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 3341 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 3342 3343 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 3344 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3345 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 3346 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3347 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 3348 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 3349 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 3350 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 3351 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 3352 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 3353 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 3354 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 3355 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 3356 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 3357 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 3358 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3359 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 3360 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3361 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 3362 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 3363 3364 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 3365 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3366 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 3367 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3368 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 3369 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 3370 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 3371 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 3372 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 3373 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 3374 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 3375 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 3376 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 3377 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 3378 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 3379 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3380 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 3381 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3382 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 3383 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 3384 3385 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 3386 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3387 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 3388 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3389 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 3390 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 3391 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 3392 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 3393 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 3394 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 3395 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 3396 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 3397 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 3398 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 3399 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 3400 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3401 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 3402 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3403 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 3404 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 3405 3406 let usesCustomInserter = 1 in { 3407 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in), 3408 "#ANDIo_1_EQ_BIT", 3409 [(set i1:$dst, (trunc (not i32:$in)))]>; 3410 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in), 3411 "#ANDIo_1_GT_BIT", 3412 [(set i1:$dst, (trunc i32:$in))]>; 3413 3414 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in), 3415 "#ANDIo_1_EQ_BIT8", 3416 [(set i1:$dst, (trunc (not i64:$in)))]>; 3417 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in), 3418 "#ANDIo_1_GT_BIT8", 3419 [(set i1:$dst, (trunc i64:$in))]>; 3420 } 3421 3422 def : Pat<(i1 (not (trunc i32:$in))), 3423 (ANDIo_1_EQ_BIT $in)>; 3424 def : Pat<(i1 (not (trunc i64:$in))), 3425 (ANDIo_1_EQ_BIT8 $in)>; 3426 3427 //===----------------------------------------------------------------------===// 3428 // PowerPC Instructions used for assembler/disassembler only 3429 // 3430 3431 // FIXME: For B=0 or B > 8, the registers following RT are used. 3432 // WARNING: Do not add patterns for this instruction without fixing this. 3433 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B), 3434 "lswi $RT, $A, $B", IIC_LdStLoad, []>; 3435 3436 // FIXME: For B=0 or B > 8, the registers following RT are used. 3437 // WARNING: Do not add patterns for this instruction without fixing this. 3438 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B), 3439 "stswi $RT, $A, $B", IIC_LdStLoad, []>; 3440 3441 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 3442 "isync", IIC_SprISYNC, []>; 3443 3444 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 3445 "icbi $src", IIC_LdStICBI, []>; 3446 3447 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name 3448 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 3449 "eieio", IIC_LdStLoad, []>; 3450 3451 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L), 3452 "wait $L", IIC_LdStLoad, []>; 3453 3454 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 3455 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 3456 3457 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 3458 "mtsr $SR, $RS", IIC_SprMTSR>; 3459 3460 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 3461 "mfsr $RS, $SR", IIC_SprMFSR>; 3462 3463 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 3464 "mtsrin $RS, $RB", IIC_SprMTSR>; 3465 3466 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 3467 "mfsrin $RS, $RB", IIC_SprMFSR>; 3468 3469 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L), 3470 "mtmsr $RS, $L", IIC_SprMTMSR>; 3471 3472 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 3473 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 3474 let L = 0; 3475 } 3476 3477 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 3478 Requires<[IsBookE]> { 3479 bits<1> E; 3480 3481 let Inst{16} = E; 3482 let Inst{21-30} = 163; 3483 } 3484 3485 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B), 3486 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 3487 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B), 3488 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 3489 3490 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 3491 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 3492 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 3493 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 3494 3495 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), 3496 "mfmsr $RT", IIC_SprMFMSR, []>; 3497 3498 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L), 3499 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 3500 3501 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 3502 "mcrfs $BF, $BFA", IIC_BrMCR>; 3503 3504 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W), 3505 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 3506 3507 def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W), 3508 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT; 3509 3510 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>; 3511 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>; 3512 3513 def MTFSF : XFLForm_1<63, 711, (outs), 3514 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), 3515 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 3516 def MTFSFo : XFLForm_1<63, 711, (outs), 3517 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), 3518 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT; 3519 3520 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 3521 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>; 3522 3523 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 3524 "slbie $RB", IIC_SprSLBIE, []>; 3525 3526 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), 3527 "slbmte $RS, $RB", IIC_SprSLBMTE, []>; 3528 3529 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), 3530 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; 3531 3532 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 3533 3534 def TLBIA : XForm_0<31, 370, (outs), (ins), 3535 "tlbia", IIC_SprTLBIA, []>; 3536 3537 def TLBSYNC : XForm_0<31, 566, (outs), (ins), 3538 "tlbsync", IIC_SprTLBSYNC, []>; 3539 3540 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 3541 "tlbiel $RB", IIC_SprTLBIEL, []>; 3542 3543 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 3544 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 3545 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 3546 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 3547 3548 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), 3549 "tlbie $RB,$RS", IIC_SprTLBIE, []>; 3550 3551 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B", 3552 IIC_LdStLoad>, Requires<[IsBookE]>; 3553 3554 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B", 3555 IIC_LdStLoad>, Requires<[IsBookE]>; 3556 3557 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 3558 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 3559 3560 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 3561 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 3562 3563 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS), 3564 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 3565 3566 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS), 3567 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 3568 3569 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 3570 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>, 3571 Requires<[IsPPC4xx]>; 3572 def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 3573 (ins gprc:$RST, gprc:$A, gprc:$B), 3574 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>, 3575 Requires<[IsPPC4xx]>, isDOT; 3576 3577 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 3578 3579 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 3580 Requires<[IsBookE]>; 3581 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 3582 Requires<[IsBookE]>; 3583 3584 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 3585 Requires<[IsE500]>; 3586 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 3587 Requires<[IsE500]>; 3588 3589 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), 3590 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 3591 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), 3592 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 3593 3594 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 3595 3596 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B), 3597 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>; 3598 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B), 3599 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>; 3600 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B), 3601 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>; 3602 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B), 3603 "ldcix $RST, $A, $B", IIC_LdStLoad, []>; 3604 3605 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 3606 "stbcix $RST, $A, $B", IIC_LdStLoad, []>; 3607 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 3608 "sthcix $RST, $A, $B", IIC_LdStLoad, []>; 3609 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 3610 "stwcix $RST, $A, $B", IIC_LdStLoad, []>; 3611 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 3612 "stdcix $RST, $A, $B", IIC_LdStLoad, []>; 3613 3614 //===----------------------------------------------------------------------===// 3615 // PowerPC Assembler Instruction Aliases 3616 // 3617 3618 // Pseudo-instructions for alternate assembly syntax (never used by codegen). 3619 // These are aliases that require C++ handling to convert to the target 3620 // instruction, while InstAliases can be handled directly by tblgen. 3621 class PPCAsmPseudo<string asm, dag iops> 3622 : Instruction { 3623 let Namespace = "PPC"; 3624 bit PPC64 = 0; // Default value, override with isPPC64 3625 3626 let OutOperandList = (outs); 3627 let InOperandList = iops; 3628 let Pattern = []; 3629 let AsmString = asm; 3630 let isAsmParserOnly = 1; 3631 let isPseudo = 1; 3632 } 3633 3634 def : InstAlias<"sc", (SC 0)>; 3635 3636 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 3637 def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 3638 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 3639 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 3640 3641 def : InstAlias<"wait", (WAIT 0)>; 3642 def : InstAlias<"waitrsv", (WAIT 1)>; 3643 def : InstAlias<"waitimpl", (WAIT 2)>; 3644 3645 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 3646 3647 def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 3648 def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 3649 3650 def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 3651 def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 3652 def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 3653 3654 def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 3655 def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 3656 def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 3657 3658 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 3659 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 3660 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 3661 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 3662 3663 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 3664 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 3665 3666 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 3667 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 3668 3669 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 3670 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 3671 3672 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 3673 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 3674 3675 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 3676 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 3677 3678 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 3679 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 3680 3681 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 3682 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 3683 3684 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 3685 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 3686 3687 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 3688 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 3689 3690 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3691 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 3692 3693 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3694 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 3695 3696 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 3697 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 3698 3699 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 3700 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 3701 3702 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 3703 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 3704 3705 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 3706 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 3707 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 3708 3709 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 3710 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 3711 3712 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 3713 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3714 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 3715 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3716 3717 def : InstAlias<"xnop", (XORI R0, R0, 0)>; 3718 3719 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3720 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3721 3722 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3723 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3724 3725 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 3726 3727 foreach BATR = 0-3 in { 3728 def : InstAlias<"mtdbatu "#BATR#", $Rx", 3729 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 3730 Requires<[IsPPC6xx]>; 3731 def : InstAlias<"mfdbatu $Rx, "#BATR, 3732 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 3733 Requires<[IsPPC6xx]>; 3734 def : InstAlias<"mtdbatl "#BATR#", $Rx", 3735 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 3736 Requires<[IsPPC6xx]>; 3737 def : InstAlias<"mfdbatl $Rx, "#BATR, 3738 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 3739 Requires<[IsPPC6xx]>; 3740 def : InstAlias<"mtibatu "#BATR#", $Rx", 3741 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 3742 Requires<[IsPPC6xx]>; 3743 def : InstAlias<"mfibatu $Rx, "#BATR, 3744 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 3745 Requires<[IsPPC6xx]>; 3746 def : InstAlias<"mtibatl "#BATR#", $Rx", 3747 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 3748 Requires<[IsPPC6xx]>; 3749 def : InstAlias<"mfibatl $Rx, "#BATR, 3750 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 3751 Requires<[IsPPC6xx]>; 3752 } 3753 3754 foreach BR = 0-7 in { 3755 def : InstAlias<"mfbr"#BR#" $Rx", 3756 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 3757 Requires<[IsPPC4xx]>; 3758 def : InstAlias<"mtbr"#BR#" $Rx", 3759 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 3760 Requires<[IsPPC4xx]>; 3761 } 3762 3763 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3764 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 3765 3766 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3767 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 3768 3769 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3770 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 3771 3772 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3773 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 3774 3775 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 3776 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 3777 3778 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3779 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 3780 3781 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 3782 3783 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 3784 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3785 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 3786 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3787 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 3788 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3789 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm", 3790 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3791 3792 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3793 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3794 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3795 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3796 3797 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 3798 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 3799 3800 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 3801 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 3802 3803 foreach SPRG = 0-3 in { 3804 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 3805 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 3806 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 3807 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 3808 } 3809 foreach SPRG = 4-7 in { 3810 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 3811 Requires<[IsBookE]>; 3812 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 3813 Requires<[IsBookE]>; 3814 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 3815 Requires<[IsBookE]>; 3816 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 3817 Requires<[IsBookE]>; 3818 } 3819 3820 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>; 3821 3822 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>; 3823 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>; 3824 3825 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 3826 3827 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>; 3828 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>; 3829 3830 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>; 3831 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>; 3832 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>; 3833 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>; 3834 3835 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 3836 3837 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 3838 Requires<[IsPPC4xx]>; 3839 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 3840 Requires<[IsPPC4xx]>; 3841 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 3842 Requires<[IsPPC4xx]>; 3843 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 3844 Requires<[IsPPC4xx]>; 3845 3846 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 3847 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3848 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 3849 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3850 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 3851 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3852 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 3853 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3854 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 3855 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3856 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 3857 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3858 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 3859 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3860 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 3861 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3862 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 3863 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3864 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 3865 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3866 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 3867 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3868 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n", 3869 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3870 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 3871 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3872 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n", 3873 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3874 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 3875 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3876 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 3877 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3878 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 3879 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 3880 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 3881 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 3882 3883 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 3884 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 3885 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 3886 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 3887 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 3888 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 3889 3890 def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 3891 def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>; 3892 // The POWER variant 3893 def : MnemonicAlias<"cntlz", "cntlzw">; 3894 def : MnemonicAlias<"cntlz.", "cntlzw.">; 3895 3896 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 3897 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3898 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 3899 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3900 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 3901 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3902 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 3903 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3904 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 3905 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3906 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 3907 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3908 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 3909 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3910 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 3911 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3912 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 3913 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3914 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n", 3915 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3916 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 3917 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3918 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n", 3919 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3920 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 3921 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3922 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 3923 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3924 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 3925 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 3926 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 3927 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 3928 3929 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 3930 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 3931 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 3932 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 3933 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 3934 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 3935 3936 def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 3937 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 3938 def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 3939 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 3940 def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 3941 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 3942 def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 3943 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 3944 def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 3945 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 3946 def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 3947 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 3948 3949 // These generic branch instruction forms are used for the assembler parser only. 3950 // Defs and Uses are conservative, since we don't know the BO value. 3951 let PPC970_Unit = 7 in { 3952 let Defs = [CTR], Uses = [CTR, RM] in { 3953 def gBC : BForm_3<16, 0, 0, (outs), 3954 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 3955 "bc $bo, $bi, $dst">; 3956 def gBCA : BForm_3<16, 1, 0, (outs), 3957 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 3958 "bca $bo, $bi, $dst">; 3959 } 3960 let Defs = [LR, CTR], Uses = [CTR, RM] in { 3961 def gBCL : BForm_3<16, 0, 1, (outs), 3962 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 3963 "bcl $bo, $bi, $dst">; 3964 def gBCLA : BForm_3<16, 1, 1, (outs), 3965 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 3966 "bcla $bo, $bi, $dst">; 3967 } 3968 let Defs = [CTR], Uses = [CTR, LR, RM] in 3969 def gBCLR : XLForm_2<19, 16, 0, (outs), 3970 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3971 "bclr $bo, $bi, $bh", IIC_BrB, []>; 3972 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 3973 def gBCLRL : XLForm_2<19, 16, 1, (outs), 3974 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3975 "bclrl $bo, $bi, $bh", IIC_BrB, []>; 3976 let Defs = [CTR], Uses = [CTR, LR, RM] in 3977 def gBCCTR : XLForm_2<19, 528, 0, (outs), 3978 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3979 "bcctr $bo, $bi, $bh", IIC_BrB, []>; 3980 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 3981 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 3982 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 3983 "bcctrl $bo, $bi, $bh", IIC_BrB, []>; 3984 } 3985 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 3986 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 3987 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 3988 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 3989 3990 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 3991 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 3992 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 3993 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 3994 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 3995 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 3996 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 3997 } 3998 multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 3999 : BranchSimpleMnemonic1<name, pm, bo> { 4000 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4001 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4002 } 4003 defm : BranchSimpleMnemonic2<"t", "", 12>; 4004 defm : BranchSimpleMnemonic2<"f", "", 4>; 4005 defm : BranchSimpleMnemonic2<"t", "-", 14>; 4006 defm : BranchSimpleMnemonic2<"f", "-", 6>; 4007 defm : BranchSimpleMnemonic2<"t", "+", 15>; 4008 defm : BranchSimpleMnemonic2<"f", "+", 7>; 4009 defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4010 defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4011 defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4012 defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4013 4014 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4015 def : InstAlias<"b"#name#pm#" $cc, $dst", 4016 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4017 def : InstAlias<"b"#name#pm#" $dst", 4018 (BCC bibo, CR0, condbrtarget:$dst)>; 4019 4020 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4021 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4022 def : InstAlias<"b"#name#"a"#pm#" $dst", 4023 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4024 4025 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4026 (BCCLR bibo, crrc:$cc)>; 4027 def : InstAlias<"b"#name#"lr"#pm, 4028 (BCCLR bibo, CR0)>; 4029 4030 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 4031 (BCCCTR bibo, crrc:$cc)>; 4032 def : InstAlias<"b"#name#"ctr"#pm, 4033 (BCCCTR bibo, CR0)>; 4034 4035 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 4036 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 4037 def : InstAlias<"b"#name#"l"#pm#" $dst", 4038 (BCCL bibo, CR0, condbrtarget:$dst)>; 4039 4040 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 4041 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4042 def : InstAlias<"b"#name#"la"#pm#" $dst", 4043 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 4044 4045 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 4046 (BCCLRL bibo, crrc:$cc)>; 4047 def : InstAlias<"b"#name#"lrl"#pm, 4048 (BCCLRL bibo, CR0)>; 4049 4050 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 4051 (BCCCTRL bibo, crrc:$cc)>; 4052 def : InstAlias<"b"#name#"ctrl"#pm, 4053 (BCCCTRL bibo, CR0)>; 4054 } 4055 multiclass BranchExtendedMnemonic<string name, int bibo> { 4056 defm : BranchExtendedMnemonicPM<name, "", bibo>; 4057 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 4058 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 4059 } 4060 defm : BranchExtendedMnemonic<"lt", 12>; 4061 defm : BranchExtendedMnemonic<"gt", 44>; 4062 defm : BranchExtendedMnemonic<"eq", 76>; 4063 defm : BranchExtendedMnemonic<"un", 108>; 4064 defm : BranchExtendedMnemonic<"so", 108>; 4065 defm : BranchExtendedMnemonic<"ge", 4>; 4066 defm : BranchExtendedMnemonic<"nl", 4>; 4067 defm : BranchExtendedMnemonic<"le", 36>; 4068 defm : BranchExtendedMnemonic<"ng", 36>; 4069 defm : BranchExtendedMnemonic<"ne", 68>; 4070 defm : BranchExtendedMnemonic<"nu", 100>; 4071 defm : BranchExtendedMnemonic<"ns", 100>; 4072 4073 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 4074 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 4075 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 4076 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 4077 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 4078 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 4079 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 4080 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 4081 4082 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 4083 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 4084 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 4085 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 4086 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 4087 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4088 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 4089 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4090 4091 multiclass TrapExtendedMnemonic<string name, int to> { 4092 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 4093 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 4094 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 4095 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 4096 } 4097 defm : TrapExtendedMnemonic<"lt", 16>; 4098 defm : TrapExtendedMnemonic<"le", 20>; 4099 defm : TrapExtendedMnemonic<"eq", 4>; 4100 defm : TrapExtendedMnemonic<"ge", 12>; 4101 defm : TrapExtendedMnemonic<"gt", 8>; 4102 defm : TrapExtendedMnemonic<"nl", 12>; 4103 defm : TrapExtendedMnemonic<"ne", 24>; 4104 defm : TrapExtendedMnemonic<"ng", 20>; 4105 defm : TrapExtendedMnemonic<"llt", 2>; 4106 defm : TrapExtendedMnemonic<"lle", 6>; 4107 defm : TrapExtendedMnemonic<"lge", 5>; 4108 defm : TrapExtendedMnemonic<"lgt", 1>; 4109 defm : TrapExtendedMnemonic<"lnl", 5>; 4110 defm : TrapExtendedMnemonic<"lng", 6>; 4111 defm : TrapExtendedMnemonic<"u", 31>; 4112 4113 // Atomic loads 4114 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>; 4115 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>; 4116 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>; 4117 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>; 4118 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>; 4119 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>; 4120 4121 // Atomic stores 4122 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>; 4123 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>; 4124 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>; 4125 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>; 4126 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>; 4127 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>; 4128
