1 //===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Type profiles 12 //===----------------------------------------------------------------------===// 13 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>; 14 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>, 15 SDTCisVT<1, i64>]>; 16 def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 17 def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 18 def SDT_ZICmp : SDTypeProfile<0, 3, 19 [SDTCisSameAs<0, 1>, 20 SDTCisVT<2, i32>]>; 21 def SDT_ZBRCCMask : SDTypeProfile<0, 3, 22 [SDTCisVT<0, i32>, 23 SDTCisVT<1, i32>, 24 SDTCisVT<2, OtherVT>]>; 25 def SDT_ZSelectCCMask : SDTypeProfile<1, 4, 26 [SDTCisSameAs<0, 1>, 27 SDTCisSameAs<1, 2>, 28 SDTCisVT<3, i32>, 29 SDTCisVT<4, i32>]>; 30 def SDT_ZWrapPtr : SDTypeProfile<1, 1, 31 [SDTCisSameAs<0, 1>, 32 SDTCisPtrTy<0>]>; 33 def SDT_ZWrapOffset : SDTypeProfile<1, 2, 34 [SDTCisSameAs<0, 1>, 35 SDTCisSameAs<0, 2>, 36 SDTCisPtrTy<0>]>; 37 def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 38 def SDT_ZExtractAccess : SDTypeProfile<1, 1, 39 [SDTCisVT<0, i32>, 40 SDTCisVT<1, i32>]>; 41 def SDT_ZGR128Binary32 : SDTypeProfile<1, 2, 42 [SDTCisVT<0, untyped>, 43 SDTCisVT<1, untyped>, 44 SDTCisVT<2, i32>]>; 45 def SDT_ZGR128Binary64 : SDTypeProfile<1, 2, 46 [SDTCisVT<0, untyped>, 47 SDTCisVT<1, untyped>, 48 SDTCisVT<2, i64>]>; 49 def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5, 50 [SDTCisVT<0, i32>, 51 SDTCisPtrTy<1>, 52 SDTCisVT<2, i32>, 53 SDTCisVT<3, i32>, 54 SDTCisVT<4, i32>, 55 SDTCisVT<5, i32>]>; 56 def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6, 57 [SDTCisVT<0, i32>, 58 SDTCisPtrTy<1>, 59 SDTCisVT<2, i32>, 60 SDTCisVT<3, i32>, 61 SDTCisVT<4, i32>, 62 SDTCisVT<5, i32>, 63 SDTCisVT<6, i32>]>; 64 def SDT_ZMemMemLength : SDTypeProfile<0, 3, 65 [SDTCisPtrTy<0>, 66 SDTCisPtrTy<1>, 67 SDTCisVT<2, i64>]>; 68 def SDT_ZMemMemLoop : SDTypeProfile<0, 4, 69 [SDTCisPtrTy<0>, 70 SDTCisPtrTy<1>, 71 SDTCisVT<2, i64>, 72 SDTCisVT<3, i64>]>; 73 def SDT_ZString : SDTypeProfile<1, 3, 74 [SDTCisPtrTy<0>, 75 SDTCisPtrTy<1>, 76 SDTCisPtrTy<2>, 77 SDTCisVT<3, i32>]>; 78 def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>; 79 def SDT_ZPrefetch : SDTypeProfile<0, 2, 80 [SDTCisVT<0, i32>, 81 SDTCisPtrTy<1>]>; 82 def SDT_ZTBegin : SDTypeProfile<0, 2, 83 [SDTCisPtrTy<0>, 84 SDTCisVT<1, i32>]>; 85 def SDT_ZInsertVectorElt : SDTypeProfile<1, 3, 86 [SDTCisVec<0>, 87 SDTCisSameAs<0, 1>, 88 SDTCisVT<3, i32>]>; 89 def SDT_ZExtractVectorElt : SDTypeProfile<1, 2, 90 [SDTCisVec<1>, 91 SDTCisVT<2, i32>]>; 92 def SDT_ZReplicate : SDTypeProfile<1, 1, 93 [SDTCisVec<0>]>; 94 def SDT_ZVecUnaryConv : SDTypeProfile<1, 1, 95 [SDTCisVec<0>, 96 SDTCisVec<1>]>; 97 def SDT_ZVecUnary : SDTypeProfile<1, 1, 98 [SDTCisVec<0>, 99 SDTCisSameAs<0, 1>]>; 100 def SDT_ZVecBinary : SDTypeProfile<1, 2, 101 [SDTCisVec<0>, 102 SDTCisSameAs<0, 1>, 103 SDTCisSameAs<0, 2>]>; 104 def SDT_ZVecBinaryInt : SDTypeProfile<1, 2, 105 [SDTCisVec<0>, 106 SDTCisSameAs<0, 1>, 107 SDTCisVT<2, i32>]>; 108 def SDT_ZVecBinaryConv : SDTypeProfile<1, 2, 109 [SDTCisVec<0>, 110 SDTCisVec<1>, 111 SDTCisSameAs<1, 2>]>; 112 def SDT_ZVecBinaryConvInt : SDTypeProfile<1, 2, 113 [SDTCisVec<0>, 114 SDTCisVec<1>, 115 SDTCisVT<2, i32>]>; 116 def SDT_ZRotateMask : SDTypeProfile<1, 2, 117 [SDTCisVec<0>, 118 SDTCisVT<1, i32>, 119 SDTCisVT<2, i32>]>; 120 def SDT_ZJoinDwords : SDTypeProfile<1, 2, 121 [SDTCisVT<0, v2i64>, 122 SDTCisVT<1, i64>, 123 SDTCisVT<2, i64>]>; 124 def SDT_ZVecTernary : SDTypeProfile<1, 3, 125 [SDTCisVec<0>, 126 SDTCisSameAs<0, 1>, 127 SDTCisSameAs<0, 2>, 128 SDTCisSameAs<0, 3>]>; 129 def SDT_ZVecTernaryInt : SDTypeProfile<1, 3, 130 [SDTCisVec<0>, 131 SDTCisSameAs<0, 1>, 132 SDTCisSameAs<0, 2>, 133 SDTCisVT<3, i32>]>; 134 def SDT_ZVecQuaternaryInt : SDTypeProfile<1, 4, 135 [SDTCisVec<0>, 136 SDTCisSameAs<0, 1>, 137 SDTCisSameAs<0, 2>, 138 SDTCisSameAs<0, 3>, 139 SDTCisVT<4, i32>]>; 140 141 //===----------------------------------------------------------------------===// 142 // Node definitions 143 //===----------------------------------------------------------------------===// 144 145 // These are target-independent nodes, but have target-specific formats. 146 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart, 147 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 148 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd, 149 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, 150 SDNPOutGlue]>; 151 def global_offset_table : SDNode<"ISD::GLOBAL_OFFSET_TABLE", SDTPtrLeaf>; 152 153 // Nodes for SystemZISD::*. See SystemZISelLowering.h for more details. 154 def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, 155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 156 def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall, 157 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 158 SDNPVariadic]>; 159 def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall, 160 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 161 SDNPVariadic]>; 162 def z_tls_gdcall : SDNode<"SystemZISD::TLS_GDCALL", SDT_ZCall, 163 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 164 SDNPVariadic]>; 165 def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall, 166 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 167 SDNPVariadic]>; 168 def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>; 169 def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET", 170 SDT_ZWrapOffset, []>; 171 def z_iabs : SDNode<"SystemZISD::IABS", SDTIntUnaryOp, []>; 172 def z_icmp : SDNode<"SystemZISD::ICMP", SDT_ZICmp, [SDNPOutGlue]>; 173 def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp, [SDNPOutGlue]>; 174 def z_tm : SDNode<"SystemZISD::TM", SDT_ZICmp, [SDNPOutGlue]>; 175 def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask, 176 [SDNPHasChain, SDNPInGlue]>; 177 def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask, 178 [SDNPInGlue]>; 179 def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>; 180 def z_extract_access : SDNode<"SystemZISD::EXTRACT_ACCESS", 181 SDT_ZExtractAccess>; 182 def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>; 183 def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>; 184 def z_sdivrem32 : SDNode<"SystemZISD::SDIVREM32", SDT_ZGR128Binary32>; 185 def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>; 186 def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>; 187 def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>; 188 189 def z_serialize : SDNode<"SystemZISD::SERIALIZE", SDTNone, 190 [SDNPHasChain, SDNPMayStore]>; 191 192 // Defined because the index is an i32 rather than a pointer. 193 def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 194 SDT_ZInsertVectorElt>; 195 def z_vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 196 SDT_ZExtractVectorElt>; 197 def z_byte_mask : SDNode<"SystemZISD::BYTE_MASK", SDT_ZReplicate>; 198 def z_rotate_mask : SDNode<"SystemZISD::ROTATE_MASK", SDT_ZRotateMask>; 199 def z_replicate : SDNode<"SystemZISD::REPLICATE", SDT_ZReplicate>; 200 def z_join_dwords : SDNode<"SystemZISD::JOIN_DWORDS", SDT_ZJoinDwords>; 201 def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>; 202 def z_merge_high : SDNode<"SystemZISD::MERGE_HIGH", SDT_ZVecBinary>; 203 def z_merge_low : SDNode<"SystemZISD::MERGE_LOW", SDT_ZVecBinary>; 204 def z_shl_double : SDNode<"SystemZISD::SHL_DOUBLE", SDT_ZVecTernaryInt>; 205 def z_permute_dwords : SDNode<"SystemZISD::PERMUTE_DWORDS", 206 SDT_ZVecTernaryInt>; 207 def z_permute : SDNode<"SystemZISD::PERMUTE", SDT_ZVecTernary>; 208 def z_pack : SDNode<"SystemZISD::PACK", SDT_ZVecBinaryConv>; 209 def z_packs_cc : SDNode<"SystemZISD::PACKS_CC", SDT_ZVecBinaryConv, 210 [SDNPOutGlue]>; 211 def z_packls_cc : SDNode<"SystemZISD::PACKLS_CC", SDT_ZVecBinaryConv, 212 [SDNPOutGlue]>; 213 def z_unpack_high : SDNode<"SystemZISD::UNPACK_HIGH", SDT_ZVecUnaryConv>; 214 def z_unpackl_high : SDNode<"SystemZISD::UNPACKL_HIGH", SDT_ZVecUnaryConv>; 215 def z_unpack_low : SDNode<"SystemZISD::UNPACK_LOW", SDT_ZVecUnaryConv>; 216 def z_unpackl_low : SDNode<"SystemZISD::UNPACKL_LOW", SDT_ZVecUnaryConv>; 217 def z_vshl_by_scalar : SDNode<"SystemZISD::VSHL_BY_SCALAR", 218 SDT_ZVecBinaryInt>; 219 def z_vsrl_by_scalar : SDNode<"SystemZISD::VSRL_BY_SCALAR", 220 SDT_ZVecBinaryInt>; 221 def z_vsra_by_scalar : SDNode<"SystemZISD::VSRA_BY_SCALAR", 222 SDT_ZVecBinaryInt>; 223 def z_vsum : SDNode<"SystemZISD::VSUM", SDT_ZVecBinaryConv>; 224 def z_vicmpe : SDNode<"SystemZISD::VICMPE", SDT_ZVecBinary>; 225 def z_vicmph : SDNode<"SystemZISD::VICMPH", SDT_ZVecBinary>; 226 def z_vicmphl : SDNode<"SystemZISD::VICMPHL", SDT_ZVecBinary>; 227 def z_vicmpes : SDNode<"SystemZISD::VICMPES", SDT_ZVecBinary, 228 [SDNPOutGlue]>; 229 def z_vicmphs : SDNode<"SystemZISD::VICMPHS", SDT_ZVecBinary, 230 [SDNPOutGlue]>; 231 def z_vicmphls : SDNode<"SystemZISD::VICMPHLS", SDT_ZVecBinary, 232 [SDNPOutGlue]>; 233 def z_vfcmpe : SDNode<"SystemZISD::VFCMPE", SDT_ZVecBinaryConv>; 234 def z_vfcmph : SDNode<"SystemZISD::VFCMPH", SDT_ZVecBinaryConv>; 235 def z_vfcmphe : SDNode<"SystemZISD::VFCMPHE", SDT_ZVecBinaryConv>; 236 def z_vfcmpes : SDNode<"SystemZISD::VFCMPES", SDT_ZVecBinaryConv, 237 [SDNPOutGlue]>; 238 def z_vfcmphs : SDNode<"SystemZISD::VFCMPHS", SDT_ZVecBinaryConv, 239 [SDNPOutGlue]>; 240 def z_vfcmphes : SDNode<"SystemZISD::VFCMPHES", SDT_ZVecBinaryConv, 241 [SDNPOutGlue]>; 242 def z_vextend : SDNode<"SystemZISD::VEXTEND", SDT_ZVecUnaryConv>; 243 def z_vround : SDNode<"SystemZISD::VROUND", SDT_ZVecUnaryConv>; 244 def z_vtm : SDNode<"SystemZISD::VTM", SDT_ZCmp, [SDNPOutGlue]>; 245 def z_vfae_cc : SDNode<"SystemZISD::VFAE_CC", SDT_ZVecTernaryInt, 246 [SDNPOutGlue]>; 247 def z_vfaez_cc : SDNode<"SystemZISD::VFAEZ_CC", SDT_ZVecTernaryInt, 248 [SDNPOutGlue]>; 249 def z_vfee_cc : SDNode<"SystemZISD::VFEE_CC", SDT_ZVecBinary, 250 [SDNPOutGlue]>; 251 def z_vfeez_cc : SDNode<"SystemZISD::VFEEZ_CC", SDT_ZVecBinary, 252 [SDNPOutGlue]>; 253 def z_vfene_cc : SDNode<"SystemZISD::VFENE_CC", SDT_ZVecBinary, 254 [SDNPOutGlue]>; 255 def z_vfenez_cc : SDNode<"SystemZISD::VFENEZ_CC", SDT_ZVecBinary, 256 [SDNPOutGlue]>; 257 def z_vistr_cc : SDNode<"SystemZISD::VISTR_CC", SDT_ZVecUnary, 258 [SDNPOutGlue]>; 259 def z_vstrc_cc : SDNode<"SystemZISD::VSTRC_CC", SDT_ZVecQuaternaryInt, 260 [SDNPOutGlue]>; 261 def z_vstrcz_cc : SDNode<"SystemZISD::VSTRCZ_CC", 262 SDT_ZVecQuaternaryInt, [SDNPOutGlue]>; 263 def z_vftci : SDNode<"SystemZISD::VFTCI", SDT_ZVecBinaryConvInt, 264 [SDNPOutGlue]>; 265 266 class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW> 267 : SDNode<"SystemZISD::"##name, profile, 268 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 269 270 def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">; 271 def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">; 272 def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">; 273 def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">; 274 def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">; 275 def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">; 276 def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">; 277 def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">; 278 def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">; 279 def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">; 280 def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">; 281 def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>; 282 283 def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength, 284 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 285 def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop, 286 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 287 def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength, 288 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 289 def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop, 290 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 291 def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength, 292 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 293 def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop, 294 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 295 def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength, 296 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 297 def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop, 298 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 299 def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength, 300 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 301 def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop, 302 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 303 def z_strcmp : SDNode<"SystemZISD::STRCMP", SDT_ZString, 304 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 305 def z_stpcpy : SDNode<"SystemZISD::STPCPY", SDT_ZString, 306 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 307 def z_search_string : SDNode<"SystemZISD::SEARCH_STRING", SDT_ZString, 308 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 309 def z_ipm : SDNode<"SystemZISD::IPM", SDT_ZI32Intrinsic, 310 [SDNPInGlue]>; 311 def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch, 312 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 313 SDNPMemOperand]>; 314 315 def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin, 316 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 317 SDNPSideEffect]>; 318 def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin, 319 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 320 SDNPSideEffect]>; 321 def z_tend : SDNode<"SystemZISD::TEND", SDTNone, 322 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 323 324 def z_vshl : SDNode<"ISD::SHL", SDT_ZVecBinary>; 325 def z_vsra : SDNode<"ISD::SRA", SDT_ZVecBinary>; 326 def z_vsrl : SDNode<"ISD::SRL", SDT_ZVecBinary>; 327 328 //===----------------------------------------------------------------------===// 329 // Pattern fragments 330 //===----------------------------------------------------------------------===// 331 332 // Signed and unsigned comparisons. 333 def z_scmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 334 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 335 return Type != SystemZICMP::UnsignedOnly; 336 }]>; 337 def z_ucmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 338 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 339 return Type != SystemZICMP::SignedOnly; 340 }]>; 341 342 // Register- and memory-based TEST UNDER MASK. 343 def z_tm_reg : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, imm)>; 344 def z_tm_mem : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, 0)>; 345 346 // Register sign-extend operations. Sub-32-bit values are represented as i32s. 347 def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>; 348 def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>; 349 def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>; 350 351 // Match extensions of an i32 to an i64, followed by an in-register sign 352 // extension from a sub-i32 value. 353 def sext8dbl : PatFrag<(ops node:$src), (sext8 (anyext node:$src))>; 354 def sext16dbl : PatFrag<(ops node:$src), (sext16 (anyext node:$src))>; 355 356 // Register zero-extend operations. Sub-32-bit values are represented as i32s. 357 def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>; 358 def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>; 359 def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>; 360 361 // Match extensions of an i32 to an i64, followed by an AND of the low 362 // i8 or i16 part. 363 def zext8dbl : PatFrag<(ops node:$src), (zext8 (anyext node:$src))>; 364 def zext16dbl : PatFrag<(ops node:$src), (zext16 (anyext node:$src))>; 365 366 // Typed floating-point loads. 367 def loadf32 : PatFrag<(ops node:$src), (f32 (load node:$src))>; 368 def loadf64 : PatFrag<(ops node:$src), (f64 (load node:$src))>; 369 370 // Extending loads in which the extension type can be signed. 371 def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 372 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 373 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD; 374 }]>; 375 def asextloadi8 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 376 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 377 }]>; 378 def asextloadi16 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 379 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 380 }]>; 381 def asextloadi32 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 382 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 383 }]>; 384 385 // Extending loads in which the extension type can be unsigned. 386 def azextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 387 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 388 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD; 389 }]>; 390 def azextloadi8 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 391 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 392 }]>; 393 def azextloadi16 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 394 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 395 }]>; 396 def azextloadi32 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 397 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 398 }]>; 399 400 // Extending loads in which the extension type doesn't matter. 401 def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 402 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD; 403 }]>; 404 def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 405 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 406 }]>; 407 def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 408 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 409 }]>; 410 def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 411 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 412 }]>; 413 414 // Aligned loads. 415 class AlignedLoad<SDPatternOperator load> 416 : PatFrag<(ops node:$addr), (load node:$addr), [{ 417 auto *Load = cast<LoadSDNode>(N); 418 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize(); 419 }]>; 420 def aligned_load : AlignedLoad<load>; 421 def aligned_asextloadi16 : AlignedLoad<asextloadi16>; 422 def aligned_asextloadi32 : AlignedLoad<asextloadi32>; 423 def aligned_azextloadi16 : AlignedLoad<azextloadi16>; 424 def aligned_azextloadi32 : AlignedLoad<azextloadi32>; 425 426 // Aligned stores. 427 class AlignedStore<SDPatternOperator store> 428 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 429 auto *Store = cast<StoreSDNode>(N); 430 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize(); 431 }]>; 432 def aligned_store : AlignedStore<store>; 433 def aligned_truncstorei16 : AlignedStore<truncstorei16>; 434 def aligned_truncstorei32 : AlignedStore<truncstorei32>; 435 436 // Non-volatile loads. Used for instructions that might access the storage 437 // location multiple times. 438 class NonvolatileLoad<SDPatternOperator load> 439 : PatFrag<(ops node:$addr), (load node:$addr), [{ 440 auto *Load = cast<LoadSDNode>(N); 441 return !Load->isVolatile(); 442 }]>; 443 def nonvolatile_load : NonvolatileLoad<load>; 444 def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>; 445 def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>; 446 def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>; 447 448 // Non-volatile stores. 449 class NonvolatileStore<SDPatternOperator store> 450 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 451 auto *Store = cast<StoreSDNode>(N); 452 return !Store->isVolatile(); 453 }]>; 454 def nonvolatile_store : NonvolatileStore<store>; 455 def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>; 456 def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>; 457 def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>; 458 459 // A store of a load that can be implemented using MVC. 460 def mvc_store : PatFrag<(ops node:$value, node:$addr), 461 (unindexedstore node:$value, node:$addr), 462 [{ return storeLoadCanUseMVC(N); }]>; 463 464 // Binary read-modify-write operations on memory in which the other 465 // operand is also memory and for which block operations like NC can 466 // be used. There are two patterns for each operator, depending on 467 // which operand contains the "other" load. 468 multiclass block_op<SDPatternOperator operator> { 469 def "1" : PatFrag<(ops node:$value, node:$addr), 470 (unindexedstore (operator node:$value, 471 (unindexedload node:$addr)), 472 node:$addr), 473 [{ return storeLoadCanUseBlockBinary(N, 0); }]>; 474 def "2" : PatFrag<(ops node:$value, node:$addr), 475 (unindexedstore (operator (unindexedload node:$addr), 476 node:$value), 477 node:$addr), 478 [{ return storeLoadCanUseBlockBinary(N, 1); }]>; 479 } 480 defm block_and : block_op<and>; 481 defm block_or : block_op<or>; 482 defm block_xor : block_op<xor>; 483 484 // Insertions. 485 def inserti8 : PatFrag<(ops node:$src1, node:$src2), 486 (or (and node:$src1, -256), node:$src2)>; 487 def insertll : PatFrag<(ops node:$src1, node:$src2), 488 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>; 489 def insertlh : PatFrag<(ops node:$src1, node:$src2), 490 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>; 491 def inserthl : PatFrag<(ops node:$src1, node:$src2), 492 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>; 493 def inserthh : PatFrag<(ops node:$src1, node:$src2), 494 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>; 495 def insertlf : PatFrag<(ops node:$src1, node:$src2), 496 (or (and node:$src1, 0xffffffff00000000), node:$src2)>; 497 def inserthf : PatFrag<(ops node:$src1, node:$src2), 498 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>; 499 500 // ORs that can be treated as insertions. 501 def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2), 502 (or node:$src1, node:$src2), [{ 503 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 504 return CurDAG->MaskedValueIsZero(N->getOperand(0), 505 APInt::getLowBitsSet(BitWidth, 8)); 506 }]>; 507 508 // ORs that can be treated as reversed insertions. 509 def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2), 510 (or node:$src1, node:$src2), [{ 511 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 512 return CurDAG->MaskedValueIsZero(N->getOperand(1), 513 APInt::getLowBitsSet(BitWidth, 8)); 514 }]>; 515 516 // Negative integer absolute. 517 def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>; 518 519 // Integer absolute, matching the canonical form generated by DAGCombiner. 520 def z_iabs32 : PatFrag<(ops node:$src), 521 (xor (add node:$src, (sra node:$src, (i32 31))), 522 (sra node:$src, (i32 31)))>; 523 def z_iabs64 : PatFrag<(ops node:$src), 524 (xor (add node:$src, (sra node:$src, (i32 63))), 525 (sra node:$src, (i32 63)))>; 526 def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>; 527 def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>; 528 529 // Integer multiply-and-add 530 def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3), 531 (add (mul node:$src1, node:$src2), node:$src3)>; 532 533 // Fused multiply-subtract, using the natural operand order. 534 def fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 535 (fma node:$src1, node:$src2, (fneg node:$src3))>; 536 537 // Fused multiply-add and multiply-subtract, but with the order of the 538 // operands matching SystemZ's MA and MS instructions. 539 def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3), 540 (fma node:$src2, node:$src3, node:$src1)>; 541 def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 542 (fma node:$src2, node:$src3, (fneg node:$src1))>; 543 544 // Floating-point negative absolute. 545 def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>; 546 547 // Create a unary operator that loads from memory and then performs 548 // the given operation on it. 549 class loadu<SDPatternOperator operator, SDPatternOperator load = load> 550 : PatFrag<(ops node:$addr), (operator (load node:$addr))>; 551 552 // Create a store operator that performs the given unary operation 553 // on the value before storing it. 554 class storeu<SDPatternOperator operator, SDPatternOperator store = store> 555 : PatFrag<(ops node:$value, node:$addr), 556 (store (operator node:$value), node:$addr)>; 557 558 // Vector representation of all-zeros and all-ones. 559 def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>; 560 def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>; 561 562 // Load a scalar and replicate it in all elements of a vector. 563 class z_replicate_load<ValueType scalartype, SDPatternOperator load> 564 : PatFrag<(ops node:$addr), 565 (z_replicate (scalartype (load node:$addr)))>; 566 def z_replicate_loadi8 : z_replicate_load<i32, anyextloadi8>; 567 def z_replicate_loadi16 : z_replicate_load<i32, anyextloadi16>; 568 def z_replicate_loadi32 : z_replicate_load<i32, load>; 569 def z_replicate_loadi64 : z_replicate_load<i64, load>; 570 def z_replicate_loadf32 : z_replicate_load<f32, load>; 571 def z_replicate_loadf64 : z_replicate_load<f64, load>; 572 573 // Load a scalar and insert it into a single element of a vector. 574 class z_vle<ValueType scalartype, SDPatternOperator load> 575 : PatFrag<(ops node:$vec, node:$addr, node:$index), 576 (z_vector_insert node:$vec, (scalartype (load node:$addr)), 577 node:$index)>; 578 def z_vlei8 : z_vle<i32, anyextloadi8>; 579 def z_vlei16 : z_vle<i32, anyextloadi16>; 580 def z_vlei32 : z_vle<i32, load>; 581 def z_vlei64 : z_vle<i64, load>; 582 def z_vlef32 : z_vle<f32, load>; 583 def z_vlef64 : z_vle<f64, load>; 584 585 // Load a scalar and insert it into the low element of the high i64 of a 586 // zeroed vector. 587 class z_vllez<ValueType scalartype, SDPatternOperator load, int index> 588 : PatFrag<(ops node:$addr), 589 (z_vector_insert (z_vzero), 590 (scalartype (load node:$addr)), (i32 index))>; 591 def z_vllezi8 : z_vllez<i32, anyextloadi8, 7>; 592 def z_vllezi16 : z_vllez<i32, anyextloadi16, 3>; 593 def z_vllezi32 : z_vllez<i32, load, 1>; 594 def z_vllezi64 : PatFrag<(ops node:$addr), 595 (z_join_dwords (i64 (load node:$addr)), (i64 0))>; 596 // We use high merges to form a v4f32 from four f32s. Propagating zero 597 // into all elements but index 1 gives this expression. 598 def z_vllezf32 : PatFrag<(ops node:$addr), 599 (bitconvert 600 (z_merge_high 601 (v2i64 602 (z_unpackl_high 603 (v4i32 604 (bitconvert 605 (v4f32 (scalar_to_vector 606 (f32 (load node:$addr)))))))), 607 (v2i64 (z_vzero))))>; 608 def z_vllezf64 : PatFrag<(ops node:$addr), 609 (z_merge_high 610 (scalar_to_vector (f64 (load node:$addr))), 611 (z_vzero))>; 612 613 // Store one element of a vector. 614 class z_vste<ValueType scalartype, SDPatternOperator store> 615 : PatFrag<(ops node:$vec, node:$addr, node:$index), 616 (store (scalartype (z_vector_extract node:$vec, node:$index)), 617 node:$addr)>; 618 def z_vstei8 : z_vste<i32, truncstorei8>; 619 def z_vstei16 : z_vste<i32, truncstorei16>; 620 def z_vstei32 : z_vste<i32, store>; 621 def z_vstei64 : z_vste<i64, store>; 622 def z_vstef32 : z_vste<f32, store>; 623 def z_vstef64 : z_vste<f64, store>; 624 625 // Arithmetic negation on vectors. 626 def z_vneg : PatFrag<(ops node:$x), (sub (z_vzero), node:$x)>; 627 628 // Bitwise negation on vectors. 629 def z_vnot : PatFrag<(ops node:$x), (xor node:$x, (z_vones))>; 630 631 // Signed "integer greater than zero" on vectors. 632 def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, (z_vzero))>; 633 634 // Signed "integer less than zero" on vectors. 635 def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph (z_vzero), node:$x)>; 636 637 // Integer absolute on vectors. 638 class z_viabs<int shift> 639 : PatFrag<(ops node:$src), 640 (xor (add node:$src, (z_vsra_by_scalar node:$src, (i32 shift))), 641 (z_vsra_by_scalar node:$src, (i32 shift)))>; 642 def z_viabs8 : z_viabs<7>; 643 def z_viabs16 : z_viabs<15>; 644 def z_viabs32 : z_viabs<31>; 645 def z_viabs64 : z_viabs<63>; 646 647 // Sign-extend the i64 elements of a vector. 648 class z_vse<int shift> 649 : PatFrag<(ops node:$src), 650 (z_vsra_by_scalar (z_vshl_by_scalar node:$src, shift), shift)>; 651 def z_vsei8 : z_vse<56>; 652 def z_vsei16 : z_vse<48>; 653 def z_vsei32 : z_vse<32>; 654 655 // ...and again with the extensions being done on individual i64 scalars. 656 class z_vse_by_parts<SDPatternOperator operator, int index1, int index2> 657 : PatFrag<(ops node:$src), 658 (z_join_dwords 659 (operator (z_vector_extract node:$src, index1)), 660 (operator (z_vector_extract node:$src, index2)))>; 661 def z_vsei8_by_parts : z_vse_by_parts<sext8dbl, 7, 15>; 662 def z_vsei16_by_parts : z_vse_by_parts<sext16dbl, 3, 7>; 663 def z_vsei32_by_parts : z_vse_by_parts<sext32, 1, 3>; 664
