1 //===- WebAssemblyInstrControl.td-WebAssembly control-flow ------*- tablegen -*- 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief WebAssembly control-flow code-gen constructs. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 let Defs = [ARGUMENTS] in { 16 17 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in { 18 // The condition operand is a boolean value which WebAssembly represents as i32. 19 def BR_IF : I<(outs), (ins I32:$cond, bb_op:$dst), 20 [(brcond I32:$cond, bb:$dst)], 21 "br_if \t$cond, $dst">; 22 let isCodeGenOnly = 1 in 23 def BR_UNLESS : I<(outs), (ins I32:$cond, bb_op:$dst), [], 24 "br_unless\t$cond, $dst">; 25 let isBarrier = 1 in { 26 def BR : I<(outs), (ins bb_op:$dst), 27 [(br bb:$dst)], 28 "br \t$dst">; 29 } // isBarrier = 1 30 } // isBranch = 1, isTerminator = 1, hasCtrlDep = 1 31 32 } // Defs = [ARGUMENTS] 33 34 def : Pat<(brcond (i32 (setne I32:$cond, 0)), bb:$dst), 35 (BR_IF I32:$cond, bb_op:$dst)>; 36 def : Pat<(brcond (i32 (seteq I32:$cond, 0)), bb:$dst), 37 (BR_UNLESS I32:$cond, bb_op:$dst)>; 38 39 let Defs = [ARGUMENTS] in { 40 41 // TODO: SelectionDAG's lowering insists on using a pointer as the index for 42 // jump tables, so in practice we don't ever use TABLESWITCH_I64 in wasm32 mode 43 // currently. 44 let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in { 45 def TABLESWITCH_I32 : I<(outs), (ins I32:$index, bb_op:$default, variable_ops), 46 [(WebAssemblytableswitch I32:$index, bb:$default)], 47 "tableswitch\t$index, $default">; 48 def TABLESWITCH_I64 : I<(outs), (ins I64:$index, bb_op:$default, variable_ops), 49 [(WebAssemblytableswitch I64:$index, bb:$default)], 50 "tableswitch\t$index, $default">; 51 } // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 52 53 // Placemarkers to indicate the start of a block or loop scope. 54 def BLOCK : I<(outs), (ins bb_op:$dst), [], "block \t$dst">; 55 def LOOP : I<(outs), (ins bb_op:$dst), [], "loop \t$dst">; 56 57 // No-op to indicate to the AsmPrinter that a loop ends here, so a 58 // basic block label is needed even if it wouldn't otherwise appear so. 59 let isTerminator = 1, hasCtrlDep = 1 in 60 def LOOP_END : I<(outs), (ins), []>; 61 62 multiclass RETURN<WebAssemblyRegClass vt> { 63 def RETURN_#vt : I<(outs), (ins vt:$val), [(WebAssemblyreturn vt:$val)], 64 "return \t$val">; 65 } 66 67 let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in { 68 let isReturn = 1 in { 69 defm : RETURN<I32>; 70 defm : RETURN<I64>; 71 defm : RETURN<F32>; 72 defm : RETURN<F64>; 73 def RETURN_VOID : I<(outs), (ins), [(WebAssemblyreturn)], "return">; 74 } // isReturn = 1 75 def UNREACHABLE : I<(outs), (ins), [(trap)], "unreachable">; 76 } // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 77 78 } // Defs = [ARGUMENTS] 79
