1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 instruction set, defining the instructions, and 11 // properties of the instructions which are needed for code generation, machine 12 // code emission, and analysis. 13 // 14 //===----------------------------------------------------------------------===// 15 16 //===----------------------------------------------------------------------===// 17 // X86 specific DAG Nodes. 18 // 19 20 def SDTIntShiftDOp: SDTypeProfile<1, 3, 21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 22 SDTCisInt<0>, SDTCisInt<3>]>; 23 24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; 25 26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 28 29 def SDTX86Cmov : SDTypeProfile<1, 4, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 32 33 // Unary and binary operator instructions that set EFLAGS as a side-effect. 34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 35 [SDTCisSameAs<0, 2>, 36 SDTCisInt<0>, SDTCisVT<1, i32>]>; 37 38 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 39 [SDTCisSameAs<0, 2>, 40 SDTCisSameAs<0, 3>, 41 SDTCisInt<0>, SDTCisVT<1, i32>]>; 42 43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 45 [SDTCisSameAs<0, 2>, 46 SDTCisSameAs<0, 3>, 47 SDTCisInt<0>, 48 SDTCisVT<1, i32>, 49 SDTCisVT<4, i32>]>; 50 // RES1, RES2, FLAGS = op LHS, RHS 51 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 52 [SDTCisSameAs<0, 1>, 53 SDTCisSameAs<0, 2>, 54 SDTCisSameAs<0, 3>, 55 SDTCisInt<0>, SDTCisVT<1, i32>]>; 56 def SDTX86BrCond : SDTypeProfile<0, 3, 57 [SDTCisVT<0, OtherVT>, 58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 59 60 def SDTX86SetCC : SDTypeProfile<1, 2, 61 [SDTCisVT<0, i8>, 62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 63 def SDTX86SetCC_C : SDTypeProfile<1, 2, 64 [SDTCisInt<0>, 65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 66 67 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 68 69 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 70 71 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 72 SDTCisVT<2, i8>]>; 73 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 74 75 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, 76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; 77 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; 78 79 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 80 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 81 SDTCisVT<1, i32>]>; 82 83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 84 85 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 86 SDTCisVT<1, iPTR>, 87 SDTCisVT<2, iPTR>]>; 88 89 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 90 SDTCisPtrTy<1>, 91 SDTCisVT<2, i32>, 92 SDTCisVT<3, i8>, 93 SDTCisVT<4, i32>]>; 94 95 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 96 97 def SDTX86Void : SDTypeProfile<0, 0, []>; 98 99 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 100 101 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 102 103 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 104 105 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 106 107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 108 109 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 110 111 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 112 113 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 114 115 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 116 [SDNPHasChain,SDNPSideEffect]>; 117 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 118 [SDNPHasChain]>; 119 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, 120 [SDNPHasChain]>; 121 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, 122 [SDNPHasChain]>; 123 124 125 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 126 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 127 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; 128 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; 129 130 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 131 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 132 133 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 134 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 135 [SDNPHasChain]>; 136 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 137 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 138 139 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; 140 141 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 142 [SDNPHasChain, SDNPSideEffect]>; 143 144 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 145 [SDNPHasChain, SDNPSideEffect]>; 146 147 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 148 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 149 SDNPMayLoad, SDNPMemOperand]>; 150 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, 151 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 152 SDNPMayLoad, SDNPMemOperand]>; 153 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, 154 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 155 SDNPMayLoad, SDNPMemOperand]>; 156 157 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 159 def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, 160 [SDNPHasChain, SDNPOptInGlue]>; 161 162 def X86vastart_save_xmm_regs : 163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 164 SDT_X86VASTART_SAVE_XMM_REGS, 165 [SDNPHasChain, SDNPVariadic]>; 166 def X86vaarg64 : 167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 169 SDNPMemOperand]>; 170 def X86callseq_start : 171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 172 [SDNPHasChain, SDNPOutGlue]>; 173 def X86callseq_end : 174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 176 177 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 179 SDNPVariadic]>; 180 181 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 183 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 185 SDNPMayLoad]>; 186 187 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, 188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 189 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, 190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 191 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, 192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 193 194 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 195 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 196 197 def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", 198 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 199 SDTCisInt<1>]>>; 200 201 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 202 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 203 204 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 206 207 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 208 [SDNPHasChain]>; 209 210 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 211 SDTypeProfile<1, 1, [SDTCisInt<0>, 212 SDTCisPtrTy<1>]>, 213 [SDNPHasChain, SDNPSideEffect]>; 214 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 215 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 216 [SDNPHasChain, SDNPSideEffect]>; 217 218 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 220 221 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 222 [SDNPCommutative]>; 223 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 224 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 225 [SDNPCommutative]>; 226 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 227 [SDNPCommutative]>; 228 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 229 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 230 231 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; 232 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; 233 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 234 [SDNPCommutative]>; 235 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 236 [SDNPCommutative]>; 237 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 238 [SDNPCommutative]>; 239 240 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; 241 242 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 243 244 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void, 245 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 246 247 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 248 [SDNPHasChain]>; 249 250 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 252 253 //===----------------------------------------------------------------------===// 254 // X86 Operand Definitions. 255 // 256 257 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 258 // the index operand of an address, to conform to x86 encoding restrictions. 259 def ptr_rc_nosp : PointerLikeRegClass<1>; 260 261 // *mem - Operand definitions for the funky X86 addressing mode operands. 262 // 263 def X86MemAsmOperand : AsmOperandClass { 264 let Name = "Mem"; 265 } 266 let RenderMethod = "addMemOperands" in { 267 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } 268 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } 269 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } 270 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } 271 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } 272 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } 273 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } 274 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } 275 // Gather mem operands 276 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; } 277 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; } 278 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; } 279 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; } 280 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; } 281 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; } 282 def X86MemVX32XOperand : AsmOperandClass { let Name = "MemVX32X"; } 283 def X86MemVY32XOperand : AsmOperandClass { let Name = "MemVY32X"; } 284 def X86MemVX64XOperand : AsmOperandClass { let Name = "MemVX64X"; } 285 def X86MemVY64XOperand : AsmOperandClass { let Name = "MemVY64X"; } 286 } 287 288 def X86AbsMemAsmOperand : AsmOperandClass { 289 let Name = "AbsMem"; 290 let SuperClasses = [X86MemAsmOperand]; 291 } 292 293 class X86MemOperand<string printMethod, 294 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> { 295 let PrintMethod = printMethod; 296 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 297 let ParserMatchClass = parserMatchClass; 298 let OperandType = "OPERAND_MEMORY"; 299 } 300 301 // Gather mem operands 302 class X86VMemOperand<RegisterClass RC, string printMethod, 303 AsmOperandClass parserMatchClass> 304 : X86MemOperand<printMethod, parserMatchClass> { 305 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm); 306 } 307 308 def anymem : X86MemOperand<"printanymem">; 309 310 def opaque32mem : X86MemOperand<"printopaquemem">; 311 def opaque48mem : X86MemOperand<"printopaquemem">; 312 def opaque80mem : X86MemOperand<"printopaquemem">; 313 def opaque512mem : X86MemOperand<"printopaquemem">; 314 315 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>; 316 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>; 317 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>; 318 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>; 319 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>; 320 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>; 321 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>; 322 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>; 323 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>; 324 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>; 325 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>; 326 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>; 327 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>; 328 329 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>; 330 331 // Gather mem operands 332 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>; 333 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>; 334 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>; 335 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>; 336 337 def vx32xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX32XOperand>; 338 def vx64xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX64XOperand>; 339 def vy32xmem : X86VMemOperand<VR256X, "printi32mem", X86MemVY32XOperand>; 340 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64XOperand>; 341 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>; 342 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>; 343 344 // A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead 345 // of a plain GPR, so that it doesn't potentially require a REX prefix. 346 def ptr_rc_norex : PointerLikeRegClass<2>; 347 def ptr_rc_norex_nosp : PointerLikeRegClass<3>; 348 349 def i8mem_NOREX : Operand<iPTR> { 350 let PrintMethod = "printi8mem"; 351 let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, i8imm); 352 let ParserMatchClass = X86Mem8AsmOperand; 353 let OperandType = "OPERAND_MEMORY"; 354 } 355 356 // GPRs available for tailcall. 357 // It represents GR32_TC, GR64_TC or GR64_TCW64. 358 def ptr_rc_tailcall : PointerLikeRegClass<4>; 359 360 // Special i32mem for addresses of load folding tail calls. These are not 361 // allowed to use callee-saved registers since they must be scheduled 362 // after callee-saved register are popped. 363 def i32mem_TC : Operand<i32> { 364 let PrintMethod = "printi32mem"; 365 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 366 i32imm, i8imm); 367 let ParserMatchClass = X86Mem32AsmOperand; 368 let OperandType = "OPERAND_MEMORY"; 369 } 370 371 // Special i64mem for addresses of load folding tail calls. These are not 372 // allowed to use callee-saved registers since they must be scheduled 373 // after callee-saved register are popped. 374 def i64mem_TC : Operand<i64> { 375 let PrintMethod = "printi64mem"; 376 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 377 ptr_rc_tailcall, i32imm, i8imm); 378 let ParserMatchClass = X86Mem64AsmOperand; 379 let OperandType = "OPERAND_MEMORY"; 380 } 381 382 let OperandType = "OPERAND_PCREL", 383 ParserMatchClass = X86AbsMemAsmOperand, 384 PrintMethod = "printPCRelImm" in { 385 def i32imm_pcrel : Operand<i32>; 386 def i16imm_pcrel : Operand<i16>; 387 388 // Branch targets have OtherVT type and print as pc-relative values. 389 def brtarget : Operand<OtherVT>; 390 def brtarget8 : Operand<OtherVT>; 391 392 } 393 394 // Special parser to detect 16-bit mode to select 16-bit displacement. 395 def X86AbsMem16AsmOperand : AsmOperandClass { 396 let Name = "AbsMem16"; 397 let RenderMethod = "addAbsMemOperands"; 398 let SuperClasses = [X86AbsMemAsmOperand]; 399 } 400 401 // Branch targets have OtherVT type and print as pc-relative values. 402 let OperandType = "OPERAND_PCREL", 403 PrintMethod = "printPCRelImm" in { 404 let ParserMatchClass = X86AbsMem16AsmOperand in 405 def brtarget16 : Operand<OtherVT>; 406 let ParserMatchClass = X86AbsMemAsmOperand in 407 def brtarget32 : Operand<OtherVT>; 408 } 409 410 let RenderMethod = "addSrcIdxOperands" in { 411 def X86SrcIdx8Operand : AsmOperandClass { 412 let Name = "SrcIdx8"; 413 let SuperClasses = [X86Mem8AsmOperand]; 414 } 415 def X86SrcIdx16Operand : AsmOperandClass { 416 let Name = "SrcIdx16"; 417 let SuperClasses = [X86Mem16AsmOperand]; 418 } 419 def X86SrcIdx32Operand : AsmOperandClass { 420 let Name = "SrcIdx32"; 421 let SuperClasses = [X86Mem32AsmOperand]; 422 } 423 def X86SrcIdx64Operand : AsmOperandClass { 424 let Name = "SrcIdx64"; 425 let SuperClasses = [X86Mem64AsmOperand]; 426 } 427 } // RenderMethod = "addSrcIdxOperands" 428 429 let RenderMethod = "addDstIdxOperands" in { 430 def X86DstIdx8Operand : AsmOperandClass { 431 let Name = "DstIdx8"; 432 let SuperClasses = [X86Mem8AsmOperand]; 433 } 434 def X86DstIdx16Operand : AsmOperandClass { 435 let Name = "DstIdx16"; 436 let SuperClasses = [X86Mem16AsmOperand]; 437 } 438 def X86DstIdx32Operand : AsmOperandClass { 439 let Name = "DstIdx32"; 440 let SuperClasses = [X86Mem32AsmOperand]; 441 } 442 def X86DstIdx64Operand : AsmOperandClass { 443 let Name = "DstIdx64"; 444 let SuperClasses = [X86Mem64AsmOperand]; 445 } 446 } // RenderMethod = "addDstIdxOperands" 447 448 let RenderMethod = "addMemOffsOperands" in { 449 def X86MemOffs16_8AsmOperand : AsmOperandClass { 450 let Name = "MemOffs16_8"; 451 let SuperClasses = [X86Mem8AsmOperand]; 452 } 453 def X86MemOffs16_16AsmOperand : AsmOperandClass { 454 let Name = "MemOffs16_16"; 455 let SuperClasses = [X86Mem16AsmOperand]; 456 } 457 def X86MemOffs16_32AsmOperand : AsmOperandClass { 458 let Name = "MemOffs16_32"; 459 let SuperClasses = [X86Mem32AsmOperand]; 460 } 461 def X86MemOffs32_8AsmOperand : AsmOperandClass { 462 let Name = "MemOffs32_8"; 463 let SuperClasses = [X86Mem8AsmOperand]; 464 } 465 def X86MemOffs32_16AsmOperand : AsmOperandClass { 466 let Name = "MemOffs32_16"; 467 let SuperClasses = [X86Mem16AsmOperand]; 468 } 469 def X86MemOffs32_32AsmOperand : AsmOperandClass { 470 let Name = "MemOffs32_32"; 471 let SuperClasses = [X86Mem32AsmOperand]; 472 } 473 def X86MemOffs32_64AsmOperand : AsmOperandClass { 474 let Name = "MemOffs32_64"; 475 let SuperClasses = [X86Mem64AsmOperand]; 476 } 477 def X86MemOffs64_8AsmOperand : AsmOperandClass { 478 let Name = "MemOffs64_8"; 479 let SuperClasses = [X86Mem8AsmOperand]; 480 } 481 def X86MemOffs64_16AsmOperand : AsmOperandClass { 482 let Name = "MemOffs64_16"; 483 let SuperClasses = [X86Mem16AsmOperand]; 484 } 485 def X86MemOffs64_32AsmOperand : AsmOperandClass { 486 let Name = "MemOffs64_32"; 487 let SuperClasses = [X86Mem32AsmOperand]; 488 } 489 def X86MemOffs64_64AsmOperand : AsmOperandClass { 490 let Name = "MemOffs64_64"; 491 let SuperClasses = [X86Mem64AsmOperand]; 492 } 493 } // RenderMethod = "addMemOffsOperands" 494 495 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 496 : X86MemOperand<printMethod, parserMatchClass> { 497 let MIOperandInfo = (ops ptr_rc, i8imm); 498 } 499 500 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 501 : X86MemOperand<printMethod, parserMatchClass> { 502 let MIOperandInfo = (ops ptr_rc); 503 } 504 505 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; 506 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; 507 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; 508 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; 509 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; 510 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; 511 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; 512 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; 513 514 class X86MemOffsOperand<Operand immOperand, string printMethod, 515 AsmOperandClass parserMatchClass> 516 : X86MemOperand<printMethod, parserMatchClass> { 517 let MIOperandInfo = (ops immOperand, i8imm); 518 } 519 520 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8", 521 X86MemOffs16_8AsmOperand>; 522 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16", 523 X86MemOffs16_16AsmOperand>; 524 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32", 525 X86MemOffs16_32AsmOperand>; 526 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8", 527 X86MemOffs32_8AsmOperand>; 528 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16", 529 X86MemOffs32_16AsmOperand>; 530 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32", 531 X86MemOffs32_32AsmOperand>; 532 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64", 533 X86MemOffs32_64AsmOperand>; 534 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8", 535 X86MemOffs64_8AsmOperand>; 536 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16", 537 X86MemOffs64_16AsmOperand>; 538 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32", 539 X86MemOffs64_32AsmOperand>; 540 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64", 541 X86MemOffs64_64AsmOperand>; 542 543 def SSECC : Operand<i8> { 544 let PrintMethod = "printSSEAVXCC"; 545 let OperandType = "OPERAND_IMMEDIATE"; 546 } 547 548 def i8immZExt3 : ImmLeaf<i8, [{ 549 return Imm >= 0 && Imm < 8; 550 }]>; 551 552 def AVXCC : Operand<i8> { 553 let PrintMethod = "printSSEAVXCC"; 554 let OperandType = "OPERAND_IMMEDIATE"; 555 } 556 557 def i8immZExt5 : ImmLeaf<i8, [{ 558 return Imm >= 0 && Imm < 32; 559 }]>; 560 561 def AVX512ICC : Operand<i8> { 562 let PrintMethod = "printSSEAVXCC"; 563 let OperandType = "OPERAND_IMMEDIATE"; 564 } 565 566 def XOPCC : Operand<i8> { 567 let PrintMethod = "printXOPCC"; 568 let OperandType = "OPERAND_IMMEDIATE"; 569 } 570 571 class ImmSExtAsmOperandClass : AsmOperandClass { 572 let SuperClasses = [ImmAsmOperand]; 573 let RenderMethod = "addImmOperands"; 574 } 575 576 def X86GR32orGR64AsmOperand : AsmOperandClass { 577 let Name = "GR32orGR64"; 578 } 579 580 def GR32orGR64 : RegisterOperand<GR32> { 581 let ParserMatchClass = X86GR32orGR64AsmOperand; 582 } 583 def AVX512RCOperand : AsmOperandClass { 584 let Name = "AVX512RC"; 585 } 586 def AVX512RC : Operand<i32> { 587 let PrintMethod = "printRoundingControl"; 588 let OperandType = "OPERAND_IMMEDIATE"; 589 let ParserMatchClass = AVX512RCOperand; 590 } 591 592 // Sign-extended immediate classes. We don't need to define the full lattice 593 // here because there is no instruction with an ambiguity between ImmSExti64i32 594 // and ImmSExti32i8. 595 // 596 // The strange ranges come from the fact that the assembler always works with 597 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 598 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 599 600 // [0, 0x7FFFFFFF] | 601 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 602 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 603 let Name = "ImmSExti64i32"; 604 } 605 606 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 607 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 608 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 609 let Name = "ImmSExti16i8"; 610 let SuperClasses = [ImmSExti64i32AsmOperand]; 611 } 612 613 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 614 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 615 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 616 let Name = "ImmSExti32i8"; 617 } 618 619 // [0, 0x0000007F] | 620 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 621 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 622 let Name = "ImmSExti64i8"; 623 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 624 ImmSExti64i32AsmOperand]; 625 } 626 627 // Unsigned immediate used by SSE/AVX instructions 628 // [0, 0xFF] 629 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 630 def ImmUnsignedi8AsmOperand : AsmOperandClass { 631 let Name = "ImmUnsignedi8"; 632 let RenderMethod = "addImmOperands"; 633 } 634 635 // A couple of more descriptive operand definitions. 636 // 16-bits but only 8 bits are significant. 637 def i16i8imm : Operand<i16> { 638 let ParserMatchClass = ImmSExti16i8AsmOperand; 639 let OperandType = "OPERAND_IMMEDIATE"; 640 } 641 // 32-bits but only 8 bits are significant. 642 def i32i8imm : Operand<i32> { 643 let ParserMatchClass = ImmSExti32i8AsmOperand; 644 let OperandType = "OPERAND_IMMEDIATE"; 645 } 646 647 // 64-bits but only 32 bits are significant. 648 def i64i32imm : Operand<i64> { 649 let ParserMatchClass = ImmSExti64i32AsmOperand; 650 let OperandType = "OPERAND_IMMEDIATE"; 651 } 652 653 // 64-bits but only 8 bits are significant. 654 def i64i8imm : Operand<i64> { 655 let ParserMatchClass = ImmSExti64i8AsmOperand; 656 let OperandType = "OPERAND_IMMEDIATE"; 657 } 658 659 // Unsigned 8-bit immediate used by SSE/AVX instructions. 660 def u8imm : Operand<i8> { 661 let PrintMethod = "printU8Imm"; 662 let ParserMatchClass = ImmUnsignedi8AsmOperand; 663 let OperandType = "OPERAND_IMMEDIATE"; 664 } 665 666 // 32-bit immediate but only 8-bits are significant and they are unsigned. 667 // Used by some SSE/AVX instructions that use intrinsics. 668 def i32u8imm : Operand<i32> { 669 let PrintMethod = "printU8Imm"; 670 let ParserMatchClass = ImmUnsignedi8AsmOperand; 671 let OperandType = "OPERAND_IMMEDIATE"; 672 } 673 674 // 64-bits but only 32 bits are significant, and those bits are treated as being 675 // pc relative. 676 def i64i32imm_pcrel : Operand<i64> { 677 let PrintMethod = "printPCRelImm"; 678 let ParserMatchClass = X86AbsMemAsmOperand; 679 let OperandType = "OPERAND_PCREL"; 680 } 681 682 def lea64_32mem : Operand<i32> { 683 let PrintMethod = "printanymem"; 684 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 685 let ParserMatchClass = X86MemAsmOperand; 686 } 687 688 // Memory operands that use 64-bit pointers in both ILP32 and LP64. 689 def lea64mem : Operand<i64> { 690 let PrintMethod = "printanymem"; 691 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 692 let ParserMatchClass = X86MemAsmOperand; 693 } 694 695 696 //===----------------------------------------------------------------------===// 697 // X86 Complex Pattern Definitions. 698 // 699 700 // Define X86-specific addressing mode. 701 def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>; 702 def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr", 703 [add, sub, mul, X86mul_imm, shl, or, frameindex], 704 []>; 705 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 706 def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr", 707 [add, sub, mul, X86mul_imm, shl, or, 708 frameindex, X86WrapperRIP], 709 []>; 710 711 def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 712 [tglobaltlsaddr], []>; 713 714 def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 715 [tglobaltlsaddr], []>; 716 717 def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr", 718 [add, sub, mul, X86mul_imm, shl, or, frameindex, 719 X86WrapperRIP], []>; 720 721 def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 722 [tglobaltlsaddr], []>; 723 724 def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 725 [tglobaltlsaddr], []>; 726 727 def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; 728 729 //===----------------------------------------------------------------------===// 730 // X86 Instruction Predicate Definitions. 731 def HasCMov : Predicate<"Subtarget->hasCMov()">; 732 def NoCMov : Predicate<"!Subtarget->hasCMov()">; 733 734 def HasMMX : Predicate<"Subtarget->hasMMX()">; 735 def Has3DNow : Predicate<"Subtarget->has3DNow()">; 736 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 737 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 738 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; 739 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 740 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; 741 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 742 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; 743 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 744 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; 745 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 746 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; 747 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; 748 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 749 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; 750 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 751 def HasAVX : Predicate<"Subtarget->hasAVX()">; 752 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 753 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; 754 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">, 755 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">; 756 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; 757 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; 758 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; 759 def HasCDI : Predicate<"Subtarget->hasCDI()">, 760 AssemblerPredicate<"FeatureCDI", "AVX-512 CD ISA">; 761 def HasPFI : Predicate<"Subtarget->hasPFI()">, 762 AssemblerPredicate<"FeaturePFI", "AVX-512 PF ISA">; 763 def HasERI : Predicate<"Subtarget->hasERI()">, 764 AssemblerPredicate<"FeatureERI", "AVX-512 ER ISA">; 765 def HasDQI : Predicate<"Subtarget->hasDQI()">, 766 AssemblerPredicate<"FeatureDQI", "AVX-512 DQ ISA">; 767 def NoDQI : Predicate<"!Subtarget->hasDQI()">; 768 def HasBWI : Predicate<"Subtarget->hasBWI()">, 769 AssemblerPredicate<"FeatureBWI", "AVX-512 BW ISA">; 770 def NoBWI : Predicate<"!Subtarget->hasBWI()">; 771 def HasVLX : Predicate<"Subtarget->hasVLX()">, 772 AssemblerPredicate<"FeatureVLX", "AVX-512 VL ISA">; 773 def NoVLX : Predicate<"!Subtarget->hasVLX()">; 774 def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">; 775 def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">; 776 def PKU : Predicate<"!Subtarget->hasPKU()">; 777 778 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 779 def HasAES : Predicate<"Subtarget->hasAES()">; 780 def HasFXSR : Predicate<"Subtarget->hasFXSR()">; 781 def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">; 782 def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">; 783 def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">; 784 def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">; 785 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; 786 def HasFMA : Predicate<"Subtarget->hasFMA()">; 787 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">; 788 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 789 def HasXOP : Predicate<"Subtarget->hasXOP()">; 790 def HasTBM : Predicate<"Subtarget->hasTBM()">; 791 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 792 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 793 def HasF16C : Predicate<"Subtarget->hasF16C()">; 794 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 795 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 796 def HasBMI : Predicate<"Subtarget->hasBMI()">; 797 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 798 def HasRTM : Predicate<"Subtarget->hasRTM()">; 799 def HasHLE : Predicate<"Subtarget->hasHLE()">; 800 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">; 801 def HasADX : Predicate<"Subtarget->hasADX()">; 802 def HasSHA : Predicate<"Subtarget->hasSHA()">; 803 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; 804 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; 805 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; 806 def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; 807 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 808 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 809 def HasMPX : Predicate<"Subtarget->hasMPX()">; 810 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; 811 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, 812 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; 813 def In64BitMode : Predicate<"Subtarget->is64Bit()">, 814 AssemblerPredicate<"Mode64Bit", "64-bit mode">; 815 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; 816 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; 817 def In16BitMode : Predicate<"Subtarget->is16Bit()">, 818 AssemblerPredicate<"Mode16Bit", "16-bit mode">; 819 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, 820 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; 821 def In32BitMode : Predicate<"Subtarget->is32Bit()">, 822 AssemblerPredicate<"Mode32Bit", "32-bit mode">; 823 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 824 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; 825 def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" 826 "Subtarget->getFrameLowering()->hasFP(*MF)">; 827 def IsPS4 : Predicate<"Subtarget->isTargetPS4()">; 828 def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">; 829 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 830 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 831 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 832 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 833 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" 834 "TM.getCodeModel() != CodeModel::Kernel">; 835 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 836 "TM.getCodeModel() == CodeModel::Kernel">; 837 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; 838 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; 839 def OptForSize : Predicate<"OptForSize">; 840 def OptForMinSize : Predicate<"OptForMinSize">; 841 def OptForSpeed : Predicate<"!OptForSize">; 842 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; 843 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; 844 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">; 845 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">; 846 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; 847 848 //===----------------------------------------------------------------------===// 849 // X86 Instruction Format Definitions. 850 // 851 852 include "X86InstrFormats.td" 853 854 //===----------------------------------------------------------------------===// 855 // Pattern fragments. 856 // 857 858 // X86 specific condition code. These correspond to CondCode in 859 // X86InstrInfo.h. They must be kept in synch. 860 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE 861 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC 862 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 863 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA 864 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 865 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE 866 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL 867 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE 868 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG 869 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ 870 def X86_COND_NO : PatLeaf<(i8 10)>; 871 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 872 def X86_COND_NS : PatLeaf<(i8 12)>; 873 def X86_COND_O : PatLeaf<(i8 13)>; 874 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE 875 def X86_COND_S : PatLeaf<(i8 15)>; 876 877 // Predicate used to help when pattern matching LZCNT/TZCNT. 878 def X86_COND_E_OR_NE : ImmLeaf<i8, [{ 879 return (Imm == X86::COND_E) || (Imm == X86::COND_NE); 880 }]>; 881 882 883 def i16immSExt8 : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>; 884 def i32immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>; 885 def i64immSExt8 : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>; 886 887 // If we have multiple users of an immediate, it's much smaller to reuse 888 // the register, rather than encode the immediate in every instruction. 889 // This has the risk of increasing register pressure from stretched live 890 // ranges, however, the immediates should be trivial to rematerialize by 891 // the RA in the event of high register pressure. 892 // TODO : This is currently enabled for stores and binary ops. There are more 893 // cases for which this can be enabled, though this catches the bulk of the 894 // issues. 895 // TODO2 : This should really also be enabled under O2, but there's currently 896 // an issue with RA where we don't pull the constants into their users 897 // when we rematerialize them. I'll follow-up on enabling O2 after we fix that 898 // issue. 899 // TODO3 : This is currently limited to single basic blocks (DAG creation 900 // pulls block immediates to the top and merges them if necessary). 901 // Eventually, it would be nice to allow ConstantHoisting to merge constants 902 // globally for potentially added savings. 903 // 904 def imm8_su : PatLeaf<(i8 imm), [{ 905 return !shouldAvoidImmediateInstFormsForSize(N); 906 }]>; 907 def imm16_su : PatLeaf<(i16 imm), [{ 908 return !shouldAvoidImmediateInstFormsForSize(N); 909 }]>; 910 def imm32_su : PatLeaf<(i32 imm), [{ 911 return !shouldAvoidImmediateInstFormsForSize(N); 912 }]>; 913 914 def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ 915 return !shouldAvoidImmediateInstFormsForSize(N); 916 }]>; 917 def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ 918 return !shouldAvoidImmediateInstFormsForSize(N); 919 }]>; 920 921 922 def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>; 923 924 925 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 926 // unsigned field. 927 def i64immZExt32 : ImmLeaf<i64, [{ return isUInt<32>(Imm); }]>; 928 929 def i64immZExt32SExt8 : ImmLeaf<i64, [{ 930 return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm)); 931 }]>; 932 933 // Helper fragments for loads. 934 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is 935 // known to be 32-bit aligned or better. Ditto for i8 to i16. 936 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 937 LoadSDNode *LD = cast<LoadSDNode>(N); 938 ISD::LoadExtType ExtType = LD->getExtensionType(); 939 if (ExtType == ISD::NON_EXTLOAD) 940 return true; 941 if (ExtType == ISD::EXTLOAD) 942 return LD->getAlignment() >= 2 && !LD->isVolatile(); 943 return false; 944 }]>; 945 946 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ 947 LoadSDNode *LD = cast<LoadSDNode>(N); 948 ISD::LoadExtType ExtType = LD->getExtensionType(); 949 if (ExtType == ISD::EXTLOAD) 950 return LD->getAlignment() >= 2 && !LD->isVolatile(); 951 return false; 952 }]>; 953 954 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 955 LoadSDNode *LD = cast<LoadSDNode>(N); 956 ISD::LoadExtType ExtType = LD->getExtensionType(); 957 if (ExtType == ISD::NON_EXTLOAD) 958 return true; 959 if (ExtType == ISD::EXTLOAD) 960 return LD->getAlignment() >= 4 && !LD->isVolatile(); 961 return false; 962 }]>; 963 964 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; 965 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 966 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 967 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 968 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 969 def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; 970 971 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 972 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 973 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 974 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 975 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 976 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 977 978 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 979 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 980 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 981 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 982 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 983 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 984 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 985 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 986 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 987 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 988 989 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 990 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 991 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 992 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 993 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 994 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 995 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 996 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 997 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 998 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 999 1000 1001 // An 'and' node with a single use. 1002 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 1003 return N->hasOneUse(); 1004 }]>; 1005 // An 'srl' node with a single use. 1006 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 1007 return N->hasOneUse(); 1008 }]>; 1009 // An 'trunc' node with a single use. 1010 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 1011 return N->hasOneUse(); 1012 }]>; 1013 1014 //===----------------------------------------------------------------------===// 1015 // Instruction list. 1016 // 1017 1018 // Nop 1019 let hasSideEffects = 0, SchedRW = [WriteZero] in { 1020 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>; 1021 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), 1022 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16; 1023 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), 1024 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32; 1025 } 1026 1027 1028 // Constructing a stack frame. 1029 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 1030 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>; 1031 1032 let SchedRW = [WriteALU] in { 1033 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in 1034 def LEAVE : I<0xC9, RawFrm, 1035 (outs), (ins), "leave", [], IIC_LEAVE>, 1036 Requires<[Not64BitMode]>; 1037 1038 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in 1039 def LEAVE64 : I<0xC9, RawFrm, 1040 (outs), (ins), "leave", [], IIC_LEAVE>, 1041 Requires<[In64BitMode]>; 1042 } // SchedRW 1043 1044 //===----------------------------------------------------------------------===// 1045 // Miscellaneous Instructions. 1046 // 1047 1048 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { 1049 let mayLoad = 1, SchedRW = [WriteLoad] in { 1050 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 1051 IIC_POP_REG16>, OpSize16; 1052 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 1053 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 1054 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 1055 IIC_POP_REG>, OpSize16; 1056 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [], 1057 IIC_POP_MEM>, OpSize16; 1058 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 1059 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 1060 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [], 1061 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>; 1062 } // mayLoad, SchedRW 1063 1064 let mayStore = 1, SchedRW = [WriteStore] in { 1065 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 1066 IIC_PUSH_REG>, OpSize16; 1067 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 1068 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 1069 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 1070 IIC_PUSH_REG>, OpSize16; 1071 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 1072 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 1073 1074 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), 1075 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16; 1076 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1077 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16; 1078 1079 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 1080 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1081 Requires<[Not64BitMode]>; 1082 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 1083 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1084 Requires<[Not64BitMode]>; 1085 } // mayStore, SchedRW 1086 1087 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { 1088 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[], 1089 IIC_PUSH_MEM>, OpSize16; 1090 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[], 1091 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>; 1092 } // mayLoad, mayStore, SchedRW 1093 1094 } 1095 1096 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0, 1097 SchedRW = [WriteLoad] in { 1098 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, 1099 OpSize16; 1100 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>, 1101 OpSize32, Requires<[Not64BitMode]>; 1102 } 1103 1104 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0, 1105 SchedRW = [WriteStore] in { 1106 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>, 1107 OpSize16; 1108 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>, 1109 OpSize32, Requires<[Not64BitMode]>; 1110 } 1111 1112 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { 1113 let mayLoad = 1, SchedRW = [WriteLoad] in { 1114 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1115 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1116 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1117 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1118 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [], 1119 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>; 1120 } // mayLoad, SchedRW 1121 let mayStore = 1, SchedRW = [WriteStore] in { 1122 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1123 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1124 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1125 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1126 } // mayStore, SchedRW 1127 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { 1128 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [], 1129 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>; 1130 } // mayLoad, mayStore, SchedRW 1131 } 1132 1133 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, 1134 SchedRW = [WriteStore] in { 1135 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 1136 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>; 1137 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 1138 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1139 Requires<[In64BitMode]>; 1140 } 1141 1142 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in 1143 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>, 1144 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; 1145 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in 1146 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>, 1147 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; 1148 1149 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 1150 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { 1151 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>, 1152 OpSize32, Requires<[Not64BitMode]>; 1153 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>, 1154 OpSize16, Requires<[Not64BitMode]>; 1155 } 1156 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 1157 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { 1158 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>, 1159 OpSize32, Requires<[Not64BitMode]>; 1160 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>, 1161 OpSize16, Requires<[Not64BitMode]>; 1162 } 1163 1164 let Constraints = "$src = $dst", SchedRW = [WriteALU] in { 1165 // GR32 = bswap GR32 1166 def BSWAP32r : I<0xC8, AddRegFrm, 1167 (outs GR32:$dst), (ins GR32:$src), 1168 "bswap{l}\t$dst", 1169 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB; 1170 1171 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 1172 "bswap{q}\t$dst", 1173 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB; 1174 } // Constraints = "$src = $dst", SchedRW 1175 1176 // Bit scan instructions. 1177 let Defs = [EFLAGS] in { 1178 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1179 "bsf{w}\t{$src, $dst|$dst, $src}", 1180 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))], 1181 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1182 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1183 "bsf{w}\t{$src, $dst|$dst, $src}", 1184 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))], 1185 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1186 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1187 "bsf{l}\t{$src, $dst|$dst, $src}", 1188 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], 1189 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1190 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1191 "bsf{l}\t{$src, $dst|$dst, $src}", 1192 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))], 1193 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1194 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1195 "bsf{q}\t{$src, $dst|$dst, $src}", 1196 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))], 1197 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1198 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1199 "bsf{q}\t{$src, $dst|$dst, $src}", 1200 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))], 1201 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1202 1203 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1204 "bsr{w}\t{$src, $dst|$dst, $src}", 1205 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], 1206 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1207 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1208 "bsr{w}\t{$src, $dst|$dst, $src}", 1209 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))], 1210 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1211 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1212 "bsr{l}\t{$src, $dst|$dst, $src}", 1213 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], 1214 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1215 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1216 "bsr{l}\t{$src, $dst|$dst, $src}", 1217 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))], 1218 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1219 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1220 "bsr{q}\t{$src, $dst|$dst, $src}", 1221 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], 1222 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1223 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1224 "bsr{q}\t{$src, $dst|$dst, $src}", 1225 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))], 1226 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1227 } // Defs = [EFLAGS] 1228 1229 let SchedRW = [WriteMicrocoded] in { 1230 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1231 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { 1232 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src), 1233 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1234 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src), 1235 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16; 1236 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src), 1237 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32; 1238 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src), 1239 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1240 } 1241 1242 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1243 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in 1244 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins), 1245 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>; 1246 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in 1247 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins), 1248 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16; 1249 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in 1250 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins), 1251 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32; 1252 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in 1253 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins), 1254 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>; 1255 1256 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1257 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in 1258 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), 1259 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>; 1260 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in 1261 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), 1262 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16; 1263 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in 1264 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), 1265 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32; 1266 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in 1267 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), 1268 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>; 1269 1270 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1271 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in { 1272 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1273 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1274 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1275 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16; 1276 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1277 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32; 1278 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1279 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1280 } 1281 } // SchedRW 1282 1283 //===----------------------------------------------------------------------===// 1284 // Move Instructions. 1285 // 1286 let SchedRW = [WriteMove] in { 1287 let hasSideEffects = 0 in { 1288 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 1289 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1290 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1291 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1292 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1293 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1294 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1295 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1296 } 1297 1298 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1299 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 1300 "mov{b}\t{$src, $dst|$dst, $src}", 1301 [(set GR8:$dst, imm:$src)], IIC_MOV>; 1302 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 1303 "mov{w}\t{$src, $dst|$dst, $src}", 1304 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16; 1305 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 1306 "mov{l}\t{$src, $dst|$dst, $src}", 1307 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32; 1308 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 1309 "mov{q}\t{$src, $dst|$dst, $src}", 1310 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>; 1311 } 1312 let isReMaterializable = 1 in { 1313 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 1314 "movabs{q}\t{$src, $dst|$dst, $src}", 1315 [(set GR64:$dst, imm:$src)], IIC_MOV>; 1316 } 1317 1318 // Longer forms that use a ModR/M byte. Needed for disassembler 1319 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 1320 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), 1321 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1322 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), 1323 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1324 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), 1325 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1326 } 1327 } // SchedRW 1328 1329 let SchedRW = [WriteStore] in { 1330 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 1331 "mov{b}\t{$src, $dst|$dst, $src}", 1332 [(store (i8 imm8_su:$src), addr:$dst)], IIC_MOV_MEM>; 1333 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 1334 "mov{w}\t{$src, $dst|$dst, $src}", 1335 [(store (i16 imm16_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16; 1336 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 1337 "mov{l}\t{$src, $dst|$dst, $src}", 1338 [(store (i32 imm32_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32; 1339 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 1340 "mov{q}\t{$src, $dst|$dst, $src}", 1341 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>; 1342 } // SchedRW 1343 1344 let hasSideEffects = 0 in { 1345 1346 /// Memory offset versions of moves. The immediate is an address mode sized 1347 /// offset from the segment base. 1348 let SchedRW = [WriteALU] in { 1349 let mayLoad = 1 in { 1350 let Defs = [AL] in 1351 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), 1352 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, 1353 AdSize32; 1354 let Defs = [AX] in 1355 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), 1356 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1357 OpSize16, AdSize32; 1358 let Defs = [EAX] in 1359 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), 1360 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1361 OpSize32, AdSize32; 1362 let Defs = [RAX] in 1363 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), 1364 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>, 1365 AdSize32; 1366 1367 let Defs = [AL] in 1368 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), 1369 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16; 1370 let Defs = [AX] in 1371 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), 1372 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1373 OpSize16, AdSize16; 1374 let Defs = [EAX] in 1375 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), 1376 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1377 AdSize16, OpSize32; 1378 } 1379 let mayStore = 1 in { 1380 let Uses = [AL] in 1381 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins), 1382 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32; 1383 let Uses = [AX] in 1384 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins), 1385 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1386 OpSize16, AdSize32; 1387 let Uses = [EAX] in 1388 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins), 1389 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1390 OpSize32, AdSize32; 1391 let Uses = [RAX] in 1392 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins), 1393 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>, 1394 AdSize32; 1395 1396 let Uses = [AL] in 1397 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins), 1398 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16; 1399 let Uses = [AX] in 1400 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins), 1401 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1402 OpSize16, AdSize16; 1403 let Uses = [EAX] in 1404 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins), 1405 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1406 OpSize32, AdSize16; 1407 } 1408 } 1409 1410 // These forms all have full 64-bit absolute addresses in their instructions 1411 // and use the movabs mnemonic to indicate this specific form. 1412 let mayLoad = 1 in { 1413 let Defs = [AL] in 1414 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), 1415 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64; 1416 let Defs = [AX] in 1417 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), 1418 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64; 1419 let Defs = [EAX] in 1420 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), 1421 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32, 1422 AdSize64; 1423 let Defs = [RAX] in 1424 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), 1425 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64; 1426 } 1427 1428 let mayStore = 1 in { 1429 let Uses = [AL] in 1430 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins), 1431 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64; 1432 let Uses = [AX] in 1433 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins), 1434 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64; 1435 let Uses = [EAX] in 1436 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins), 1437 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32, 1438 AdSize64; 1439 let Uses = [RAX] in 1440 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins), 1441 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64; 1442 } 1443 } // hasSideEffects = 0 1444 1445 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, 1446 SchedRW = [WriteMove] in { 1447 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 1448 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1449 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1450 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1451 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1452 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1453 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1454 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1455 } 1456 1457 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 1458 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 1459 "mov{b}\t{$src, $dst|$dst, $src}", 1460 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>; 1461 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1462 "mov{w}\t{$src, $dst|$dst, $src}", 1463 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16; 1464 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1465 "mov{l}\t{$src, $dst|$dst, $src}", 1466 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; 1467 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1468 "mov{q}\t{$src, $dst|$dst, $src}", 1469 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>; 1470 } 1471 1472 let SchedRW = [WriteStore] in { 1473 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 1474 "mov{b}\t{$src, $dst|$dst, $src}", 1475 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; 1476 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1477 "mov{w}\t{$src, $dst|$dst, $src}", 1478 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16; 1479 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1480 "mov{l}\t{$src, $dst|$dst, $src}", 1481 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32; 1482 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1483 "mov{q}\t{$src, $dst|$dst, $src}", 1484 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>; 1485 } // SchedRW 1486 1487 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 1488 // that they can be used for copying and storing h registers, which can't be 1489 // encoded when a REX prefix is present. 1490 let isCodeGenOnly = 1 in { 1491 let hasSideEffects = 0 in 1492 def MOV8rr_NOREX : I<0x88, MRMDestReg, 1493 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1494 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>, 1495 Sched<[WriteMove]>; 1496 let mayStore = 1, hasSideEffects = 0 in 1497 def MOV8mr_NOREX : I<0x88, MRMDestMem, 1498 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1499 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1500 IIC_MOV_MEM>, Sched<[WriteStore]>; 1501 let mayLoad = 1, hasSideEffects = 0, 1502 canFoldAsLoad = 1, isReMaterializable = 1 in 1503 def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1504 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1505 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1506 IIC_MOV_MEM>, Sched<[WriteLoad]>; 1507 } 1508 1509 1510 // Condition code ops, incl. set if equal/not equal/... 1511 let SchedRW = [WriteALU] in { 1512 let Defs = [EFLAGS], Uses = [AH] in 1513 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", 1514 [(set EFLAGS, (X86sahf AH))], IIC_AHF>, 1515 Requires<[HasLAHFSAHF]>; 1516 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in 1517 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [], 1518 IIC_AHF>, // AH = flags 1519 Requires<[HasLAHFSAHF]>; 1520 } // SchedRW 1521 1522 //===----------------------------------------------------------------------===// 1523 // Bit tests instructions: BT, BTS, BTR, BTC. 1524 1525 let Defs = [EFLAGS] in { 1526 let SchedRW = [WriteALU] in { 1527 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1528 "bt{w}\t{$src2, $src1|$src1, $src2}", 1529 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>, 1530 OpSize16, TB; 1531 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1532 "bt{l}\t{$src2, $src1|$src1, $src2}", 1533 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, 1534 OpSize32, TB; 1535 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1536 "bt{q}\t{$src2, $src1|$src1, $src2}", 1537 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB; 1538 } // SchedRW 1539 1540 // Unlike with the register+register form, the memory+register form of the 1541 // bt instruction does not ignore the high bits of the index. From ISel's 1542 // perspective, this is pretty bizarre. Make these instructions disassembly 1543 // only for now. 1544 1545 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { 1546 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1547 "bt{w}\t{$src2, $src1|$src1, $src2}", 1548 // [(X86bt (loadi16 addr:$src1), GR16:$src2), 1549 // (implicit EFLAGS)] 1550 [], IIC_BT_MR 1551 >, OpSize16, TB, Requires<[FastBTMem]>; 1552 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1553 "bt{l}\t{$src2, $src1|$src1, $src2}", 1554 // [(X86bt (loadi32 addr:$src1), GR32:$src2), 1555 // (implicit EFLAGS)] 1556 [], IIC_BT_MR 1557 >, OpSize32, TB, Requires<[FastBTMem]>; 1558 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1559 "bt{q}\t{$src2, $src1|$src1, $src2}", 1560 // [(X86bt (loadi64 addr:$src1), GR64:$src2), 1561 // (implicit EFLAGS)] 1562 [], IIC_BT_MR 1563 >, TB; 1564 } 1565 1566 let SchedRW = [WriteALU] in { 1567 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1568 "bt{w}\t{$src2, $src1|$src1, $src2}", 1569 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))], 1570 IIC_BT_RI>, OpSize16, TB; 1571 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1572 "bt{l}\t{$src2, $src1|$src1, $src2}", 1573 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))], 1574 IIC_BT_RI>, OpSize32, TB; 1575 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1576 "bt{q}\t{$src2, $src1|$src1, $src2}", 1577 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))], 1578 IIC_BT_RI>, TB; 1579 } // SchedRW 1580 1581 // Note that these instructions don't need FastBTMem because that 1582 // only applies when the other operand is in a register. When it's 1583 // an immediate, bt is still fast. 1584 let SchedRW = [WriteALU] in { 1585 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1586 "bt{w}\t{$src2, $src1|$src1, $src2}", 1587 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) 1588 ], IIC_BT_MI>, OpSize16, TB; 1589 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1590 "bt{l}\t{$src2, $src1|$src1, $src2}", 1591 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) 1592 ], IIC_BT_MI>, OpSize32, TB; 1593 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1594 "bt{q}\t{$src2, $src1|$src1, $src2}", 1595 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1596 i64immSExt8:$src2))], IIC_BT_MI>, TB; 1597 } // SchedRW 1598 1599 let hasSideEffects = 0 in { 1600 let SchedRW = [WriteALU] in { 1601 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1602 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1603 OpSize16, TB; 1604 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1605 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1606 OpSize32, TB; 1607 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1608 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1609 } // SchedRW 1610 1611 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1612 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1613 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1614 OpSize16, TB; 1615 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1616 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1617 OpSize32, TB; 1618 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1619 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1620 } 1621 1622 let SchedRW = [WriteALU] in { 1623 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1624 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1625 OpSize16, TB; 1626 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1627 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1628 OpSize32, TB; 1629 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1630 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1631 } // SchedRW 1632 1633 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1634 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1635 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1636 OpSize16, TB; 1637 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1638 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1639 OpSize32, TB; 1640 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1641 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1642 } 1643 1644 let SchedRW = [WriteALU] in { 1645 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1646 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1647 OpSize16, TB; 1648 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1649 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1650 OpSize32, TB; 1651 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1652 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1653 } // SchedRW 1654 1655 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1656 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1657 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1658 OpSize16, TB; 1659 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1660 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1661 OpSize32, TB; 1662 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1663 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1664 } 1665 1666 let SchedRW = [WriteALU] in { 1667 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1668 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1669 OpSize16, TB; 1670 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1671 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1672 OpSize32, TB; 1673 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1674 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1675 } // SchedRW 1676 1677 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1678 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1679 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1680 OpSize16, TB; 1681 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1682 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1683 OpSize32, TB; 1684 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1685 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1686 } 1687 1688 let SchedRW = [WriteALU] in { 1689 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1690 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1691 OpSize16, TB; 1692 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1693 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1694 OpSize32, TB; 1695 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1696 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1697 } // SchedRW 1698 1699 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1700 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1701 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1702 OpSize16, TB; 1703 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1704 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1705 OpSize32, TB; 1706 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1707 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1708 } 1709 1710 let SchedRW = [WriteALU] in { 1711 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1712 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1713 OpSize16, TB; 1714 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1715 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1716 OpSize32, TB; 1717 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1718 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1719 } // SchedRW 1720 1721 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1722 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1723 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1724 OpSize16, TB; 1725 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1726 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1727 OpSize32, TB; 1728 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1729 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1730 } 1731 } // hasSideEffects = 0 1732 } // Defs = [EFLAGS] 1733 1734 1735 //===----------------------------------------------------------------------===// 1736 // Atomic support 1737 // 1738 1739 // Atomic swap. These are just normal xchg instructions. But since a memory 1740 // operand is referenced, the atomicity is ensured. 1741 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag, 1742 InstrItinClass itin> { 1743 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 1744 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 1745 (ins GR8:$val, i8mem:$ptr), 1746 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 1747 [(set 1748 GR8:$dst, 1749 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 1750 itin>; 1751 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 1752 (ins GR16:$val, i16mem:$ptr), 1753 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 1754 [(set 1755 GR16:$dst, 1756 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 1757 itin>, OpSize16; 1758 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 1759 (ins GR32:$val, i32mem:$ptr), 1760 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 1761 [(set 1762 GR32:$dst, 1763 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 1764 itin>, OpSize32; 1765 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 1766 (ins GR64:$val, i64mem:$ptr), 1767 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 1768 [(set 1769 GR64:$dst, 1770 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 1771 itin>; 1772 } 1773 } 1774 1775 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>; 1776 1777 // Swap between registers. 1778 let SchedRW = [WriteALU] in { 1779 let Constraints = "$val = $dst" in { 1780 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), 1781 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1782 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), 1783 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1784 OpSize16; 1785 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), 1786 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1787 OpSize32; 1788 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), 1789 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1790 } 1791 1792 // Swap between EAX and other registers. 1793 let Uses = [AX], Defs = [AX] in 1794 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), 1795 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16; 1796 let Uses = [EAX], Defs = [EAX] in 1797 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), 1798 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1799 OpSize32, Requires<[Not64BitMode]>; 1800 let Uses = [EAX], Defs = [EAX] in 1801 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding. 1802 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP. 1803 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src), 1804 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1805 OpSize32, Requires<[In64BitMode]>; 1806 let Uses = [RAX], Defs = [RAX] in 1807 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), 1808 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>; 1809 } // SchedRW 1810 1811 let SchedRW = [WriteALU] in { 1812 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1813 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1814 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1815 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1816 OpSize16; 1817 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1818 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1819 OpSize32; 1820 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1821 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1822 } // SchedRW 1823 1824 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1825 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1826 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1827 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1828 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1829 OpSize16; 1830 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1831 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1832 OpSize32; 1833 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1834 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1835 1836 } 1837 1838 let SchedRW = [WriteALU] in { 1839 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1840 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1841 IIC_CMPXCHG_REG8>, TB; 1842 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1843 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1844 IIC_CMPXCHG_REG>, TB, OpSize16; 1845 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1846 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1847 IIC_CMPXCHG_REG>, TB, OpSize32; 1848 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1849 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1850 IIC_CMPXCHG_REG>, TB; 1851 } // SchedRW 1852 1853 let SchedRW = [WriteALULd, WriteRMW] in { 1854 let mayLoad = 1, mayStore = 1 in { 1855 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1856 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1857 IIC_CMPXCHG_MEM8>, TB; 1858 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1859 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1860 IIC_CMPXCHG_MEM>, TB, OpSize16; 1861 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1862 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1863 IIC_CMPXCHG_MEM>, TB, OpSize32; 1864 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1865 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1866 IIC_CMPXCHG_MEM>, TB; 1867 } 1868 1869 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 1870 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 1871 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB; 1872 1873 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 1874 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 1875 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>, 1876 TB, Requires<[HasCmpxchg16b]>; 1877 } // SchedRW 1878 1879 1880 // Lock instruction prefix 1881 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; 1882 1883 // Rex64 instruction prefix 1884 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, 1885 Requires<[In64BitMode]>; 1886 1887 // Data16 instruction prefix 1888 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; 1889 1890 // Repeat string operation instruction prefixes 1891 // These uses the DF flag in the EFLAGS register to inc or dec ECX 1892 let Defs = [ECX], Uses = [ECX,EFLAGS] in { 1893 // Repeat (used with INS, OUTS, MOVS, LODS and STOS) 1894 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; 1895 // Repeat while not equal (used with CMPS and SCAS) 1896 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; 1897 } 1898 1899 1900 // String manipulation instructions 1901 let SchedRW = [WriteMicrocoded] in { 1902 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1903 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in 1904 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), 1905 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>; 1906 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in 1907 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), 1908 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16; 1909 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in 1910 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), 1911 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32; 1912 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in 1913 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), 1914 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>; 1915 } 1916 1917 let SchedRW = [WriteSystem] in { 1918 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1919 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in { 1920 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), 1921 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>; 1922 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), 1923 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16; 1924 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), 1925 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32; 1926 } 1927 1928 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1929 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in { 1930 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins), 1931 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>; 1932 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins), 1933 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16; 1934 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins), 1935 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32; 1936 } 1937 } 1938 1939 // Flag instructions 1940 let SchedRW = [WriteALU] in { 1941 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>; 1942 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>; 1943 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>; 1944 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>; 1945 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>; 1946 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>; 1947 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>; 1948 1949 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB; 1950 } 1951 1952 // Table lookup instructions 1953 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>, 1954 Sched<[WriteLoad]>; 1955 1956 let SchedRW = [WriteMicrocoded] in { 1957 // ASCII Adjust After Addition 1958 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1959 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>, 1960 Requires<[Not64BitMode]>; 1961 1962 // ASCII Adjust AX Before Division 1963 // sets AL, AH and EFLAGS and uses AL and AH 1964 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 1965 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>; 1966 1967 // ASCII Adjust AX After Multiply 1968 // sets AL, AH and EFLAGS and uses AL 1969 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 1970 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>; 1971 1972 // ASCII Adjust AL After Subtraction - sets 1973 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1974 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>, 1975 Requires<[Not64BitMode]>; 1976 1977 // Decimal Adjust AL after Addition 1978 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1979 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>, 1980 Requires<[Not64BitMode]>; 1981 1982 // Decimal Adjust AL after Subtraction 1983 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1984 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>, 1985 Requires<[Not64BitMode]>; 1986 } // SchedRW 1987 1988 let SchedRW = [WriteSystem] in { 1989 // Check Array Index Against Bounds 1990 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1991 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16, 1992 Requires<[Not64BitMode]>; 1993 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1994 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32, 1995 Requires<[Not64BitMode]>; 1996 1997 // Adjust RPL Field of Segment Selector 1998 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1999 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>, 2000 Requires<[Not64BitMode]>; 2001 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2002 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>, 2003 Requires<[Not64BitMode]>; 2004 } // SchedRW 2005 2006 //===----------------------------------------------------------------------===// 2007 // MOVBE Instructions 2008 // 2009 let Predicates = [HasMOVBE] in { 2010 let SchedRW = [WriteALULd] in { 2011 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2012 "movbe{w}\t{$src, $dst|$dst, $src}", 2013 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>, 2014 OpSize16, T8PS; 2015 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2016 "movbe{l}\t{$src, $dst|$dst, $src}", 2017 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>, 2018 OpSize32, T8PS; 2019 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2020 "movbe{q}\t{$src, $dst|$dst, $src}", 2021 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>, 2022 T8PS; 2023 } 2024 let SchedRW = [WriteStore] in { 2025 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2026 "movbe{w}\t{$src, $dst|$dst, $src}", 2027 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>, 2028 OpSize16, T8PS; 2029 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2030 "movbe{l}\t{$src, $dst|$dst, $src}", 2031 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>, 2032 OpSize32, T8PS; 2033 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2034 "movbe{q}\t{$src, $dst|$dst, $src}", 2035 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>, 2036 T8PS; 2037 } 2038 } 2039 2040 //===----------------------------------------------------------------------===// 2041 // RDRAND Instruction 2042 // 2043 let Predicates = [HasRDRAND], Defs = [EFLAGS] in { 2044 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 2045 "rdrand{w}\t$dst", 2046 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB; 2047 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 2048 "rdrand{l}\t$dst", 2049 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB; 2050 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 2051 "rdrand{q}\t$dst", 2052 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB; 2053 } 2054 2055 //===----------------------------------------------------------------------===// 2056 // RDSEED Instruction 2057 // 2058 let Predicates = [HasRDSEED], Defs = [EFLAGS] in { 2059 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), 2060 "rdseed{w}\t$dst", 2061 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB; 2062 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), 2063 "rdseed{l}\t$dst", 2064 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB; 2065 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), 2066 "rdseed{q}\t$dst", 2067 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB; 2068 } 2069 2070 //===----------------------------------------------------------------------===// 2071 // LZCNT Instruction 2072 // 2073 let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 2074 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2075 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2076 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS, 2077 OpSize16; 2078 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2079 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2080 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 2081 (implicit EFLAGS)]>, XS, OpSize16; 2082 2083 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2084 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2085 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS, 2086 OpSize32; 2087 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2088 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2089 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 2090 (implicit EFLAGS)]>, XS, OpSize32; 2091 2092 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2093 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2094 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 2095 XS; 2096 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2097 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2098 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 2099 (implicit EFLAGS)]>, XS; 2100 } 2101 2102 let Predicates = [HasLZCNT] in { 2103 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE), 2104 (X86cmp GR16:$src, (i16 0))), 2105 (LZCNT16rr GR16:$src)>; 2106 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE), 2107 (X86cmp GR32:$src, (i32 0))), 2108 (LZCNT32rr GR32:$src)>; 2109 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE), 2110 (X86cmp GR64:$src, (i64 0))), 2111 (LZCNT64rr GR64:$src)>; 2112 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE), 2113 (X86cmp GR16:$src, (i16 0))), 2114 (LZCNT16rr GR16:$src)>; 2115 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE), 2116 (X86cmp GR32:$src, (i32 0))), 2117 (LZCNT32rr GR32:$src)>; 2118 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE), 2119 (X86cmp GR64:$src, (i64 0))), 2120 (LZCNT64rr GR64:$src)>; 2121 2122 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE), 2123 (X86cmp (loadi16 addr:$src), (i16 0))), 2124 (LZCNT16rm addr:$src)>; 2125 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE), 2126 (X86cmp (loadi32 addr:$src), (i32 0))), 2127 (LZCNT32rm addr:$src)>; 2128 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE), 2129 (X86cmp (loadi64 addr:$src), (i64 0))), 2130 (LZCNT64rm addr:$src)>; 2131 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE), 2132 (X86cmp (loadi16 addr:$src), (i16 0))), 2133 (LZCNT16rm addr:$src)>; 2134 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE), 2135 (X86cmp (loadi32 addr:$src), (i32 0))), 2136 (LZCNT32rm addr:$src)>; 2137 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE), 2138 (X86cmp (loadi64 addr:$src), (i64 0))), 2139 (LZCNT64rm addr:$src)>; 2140 } 2141 2142 //===----------------------------------------------------------------------===// 2143 // BMI Instructions 2144 // 2145 let Predicates = [HasBMI], Defs = [EFLAGS] in { 2146 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2147 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2148 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS, 2149 OpSize16; 2150 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2151 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2152 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 2153 (implicit EFLAGS)]>, XS, OpSize16; 2154 2155 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2156 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2157 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS, 2158 OpSize32; 2159 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2160 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2161 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 2162 (implicit EFLAGS)]>, XS, OpSize32; 2163 2164 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2165 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2166 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 2167 XS; 2168 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2169 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2170 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 2171 (implicit EFLAGS)]>, XS; 2172 } 2173 2174 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 2175 RegisterClass RC, X86MemOperand x86memop> { 2176 let hasSideEffects = 0 in { 2177 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 2178 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2179 []>, T8PS, VEX_4V; 2180 let mayLoad = 1 in 2181 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 2182 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2183 []>, T8PS, VEX_4V; 2184 } 2185 } 2186 2187 let Predicates = [HasBMI], Defs = [EFLAGS] in { 2188 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; 2189 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; 2190 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; 2191 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; 2192 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; 2193 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; 2194 } 2195 2196 //===----------------------------------------------------------------------===// 2197 // Pattern fragments to auto generate BMI instructions. 2198 //===----------------------------------------------------------------------===// 2199 2200 let Predicates = [HasBMI] in { 2201 // FIXME: patterns for the load versions are not implemented 2202 def : Pat<(and GR32:$src, (add GR32:$src, -1)), 2203 (BLSR32rr GR32:$src)>; 2204 def : Pat<(and GR64:$src, (add GR64:$src, -1)), 2205 (BLSR64rr GR64:$src)>; 2206 2207 def : Pat<(xor GR32:$src, (add GR32:$src, -1)), 2208 (BLSMSK32rr GR32:$src)>; 2209 def : Pat<(xor GR64:$src, (add GR64:$src, -1)), 2210 (BLSMSK64rr GR64:$src)>; 2211 2212 def : Pat<(and GR32:$src, (ineg GR32:$src)), 2213 (BLSI32rr GR32:$src)>; 2214 def : Pat<(and GR64:$src, (ineg GR64:$src)), 2215 (BLSI64rr GR64:$src)>; 2216 } 2217 2218 let Predicates = [HasBMI] in { 2219 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE), 2220 (X86cmp GR16:$src, (i16 0))), 2221 (TZCNT16rr GR16:$src)>; 2222 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE), 2223 (X86cmp GR32:$src, (i32 0))), 2224 (TZCNT32rr GR32:$src)>; 2225 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE), 2226 (X86cmp GR64:$src, (i64 0))), 2227 (TZCNT64rr GR64:$src)>; 2228 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE), 2229 (X86cmp GR16:$src, (i16 0))), 2230 (TZCNT16rr GR16:$src)>; 2231 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE), 2232 (X86cmp GR32:$src, (i32 0))), 2233 (TZCNT32rr GR32:$src)>; 2234 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE), 2235 (X86cmp GR64:$src, (i64 0))), 2236 (TZCNT64rr GR64:$src)>; 2237 2238 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE), 2239 (X86cmp (loadi16 addr:$src), (i16 0))), 2240 (TZCNT16rm addr:$src)>; 2241 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE), 2242 (X86cmp (loadi32 addr:$src), (i32 0))), 2243 (TZCNT32rm addr:$src)>; 2244 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE), 2245 (X86cmp (loadi64 addr:$src), (i64 0))), 2246 (TZCNT64rm addr:$src)>; 2247 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE), 2248 (X86cmp (loadi16 addr:$src), (i16 0))), 2249 (TZCNT16rm addr:$src)>; 2250 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE), 2251 (X86cmp (loadi32 addr:$src), (i32 0))), 2252 (TZCNT32rm addr:$src)>; 2253 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE), 2254 (X86cmp (loadi64 addr:$src), (i64 0))), 2255 (TZCNT64rm addr:$src)>; 2256 } 2257 2258 2259 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 2260 X86MemOperand x86memop, Intrinsic Int, 2261 PatFrag ld_frag> { 2262 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2263 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2264 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2265 T8PS, VEX_4VOp3; 2266 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2267 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2268 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 2269 (implicit EFLAGS)]>, T8PS, VEX_4VOp3; 2270 } 2271 2272 let Predicates = [HasBMI], Defs = [EFLAGS] in { 2273 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem, 2274 int_x86_bmi_bextr_32, loadi32>; 2275 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem, 2276 int_x86_bmi_bextr_64, loadi64>, VEX_W; 2277 } 2278 2279 let Predicates = [HasBMI2], Defs = [EFLAGS] in { 2280 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 2281 int_x86_bmi_bzhi_32, loadi32>; 2282 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 2283 int_x86_bmi_bzhi_64, loadi64>, VEX_W; 2284 } 2285 2286 2287 def CountTrailingOnes : SDNodeXForm<imm, [{ 2288 // Count the trailing ones in the immediate. 2289 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N)); 2290 }]>; 2291 2292 def BZHIMask : ImmLeaf<i64, [{ 2293 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32); 2294 }]>; 2295 2296 let Predicates = [HasBMI2] in { 2297 def : Pat<(and GR64:$src, BZHIMask:$mask), 2298 (BZHI64rr GR64:$src, 2299 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2300 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2301 2302 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)), 2303 (BZHI32rr GR32:$src, 2304 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2305 2306 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)), 2307 (BZHI32rm addr:$src, 2308 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2309 2310 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)), 2311 (BZHI64rr GR64:$src, 2312 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2313 2314 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)), 2315 (BZHI64rm addr:$src, 2316 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2317 } // HasBMI2 2318 2319 let Predicates = [HasBMI] in { 2320 def : Pat<(X86bextr GR32:$src1, GR32:$src2), 2321 (BEXTR32rr GR32:$src1, GR32:$src2)>; 2322 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2), 2323 (BEXTR32rm addr:$src1, GR32:$src2)>; 2324 def : Pat<(X86bextr GR64:$src1, GR64:$src2), 2325 (BEXTR64rr GR64:$src1, GR64:$src2)>; 2326 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2), 2327 (BEXTR64rm addr:$src1, GR64:$src2)>; 2328 } // HasBMI 2329 2330 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 2331 X86MemOperand x86memop, Intrinsic Int, 2332 PatFrag ld_frag> { 2333 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2334 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2335 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, 2336 VEX_4V; 2337 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2338 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2339 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V; 2340 } 2341 2342 let Predicates = [HasBMI2] in { 2343 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 2344 int_x86_bmi_pdep_32, loadi32>, T8XD; 2345 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 2346 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; 2347 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 2348 int_x86_bmi_pext_32, loadi32>, T8XS; 2349 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 2350 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; 2351 } 2352 2353 //===----------------------------------------------------------------------===// 2354 // TBM Instructions 2355 // 2356 let Predicates = [HasTBM], Defs = [EFLAGS] in { 2357 2358 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr, 2359 X86MemOperand x86memop, PatFrag ld_frag, 2360 Intrinsic Int, Operand immtype, 2361 SDPatternOperator immoperator> { 2362 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2363 !strconcat(OpcodeStr, 2364 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2365 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>, 2366 XOP, XOPA; 2367 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst), 2368 (ins x86memop:$src1, immtype:$cntl), 2369 !strconcat(OpcodeStr, 2370 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2371 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>, 2372 XOP, XOPA; 2373 } 2374 2375 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32, 2376 int_x86_tbm_bextri_u32, i32imm, imm>; 2377 let ImmT = Imm32S in 2378 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64, 2379 int_x86_tbm_bextri_u64, i64i32imm, 2380 i64immSExt32>, VEX_W; 2381 2382 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem, 2383 RegisterClass RC, string OpcodeStr, 2384 X86MemOperand x86memop, PatFrag ld_frag> { 2385 let hasSideEffects = 0 in { 2386 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src), 2387 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2388 []>, XOP_4V, XOP9; 2389 let mayLoad = 1 in 2390 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src), 2391 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2392 []>, XOP_4V, XOP9; 2393 } 2394 } 2395 2396 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr, 2397 Format FormReg, Format FormMem> { 2398 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem, 2399 loadi32>; 2400 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem, 2401 loadi64>, VEX_W; 2402 } 2403 2404 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>; 2405 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>; 2406 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>; 2407 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>; 2408 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>; 2409 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>; 2410 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>; 2411 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>; 2412 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>; 2413 } // HasTBM, EFLAGS 2414 2415 //===----------------------------------------------------------------------===// 2416 // MONITORX/MWAITX Instructions 2417 // 2418 let SchedRW = [WriteSystem] in { 2419 let Uses = [EAX, ECX, EDX] in 2420 def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", [], 2421 IIC_SSE_MONITOR>, TB; 2422 let Uses = [ECX, EAX, EBX] in 2423 def MWAITXrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", [], IIC_SSE_MWAIT>, 2424 TB; 2425 } // SchedRW 2426 2427 def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrr)>, Requires<[Not64BitMode]>; 2428 def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrr)>, Requires<[In64BitMode]>; 2429 2430 def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>, 2431 Requires<[Not64BitMode]>; 2432 def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>, 2433 Requires<[In64BitMode]>; 2434 2435 //===----------------------------------------------------------------------===// 2436 // CLZERO Instruction 2437 // 2438 let Uses = [EAX] in 2439 def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, TB; 2440 2441 //===----------------------------------------------------------------------===// 2442 // Pattern fragments to auto generate TBM instructions. 2443 //===----------------------------------------------------------------------===// 2444 2445 let Predicates = [HasTBM] in { 2446 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)), 2447 (BEXTRI32ri GR32:$src1, imm:$src2)>; 2448 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)), 2449 (BEXTRI32mi addr:$src1, imm:$src2)>; 2450 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2), 2451 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>; 2452 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2), 2453 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>; 2454 2455 // FIXME: patterns for the load versions are not implemented 2456 def : Pat<(and GR32:$src, (add GR32:$src, 1)), 2457 (BLCFILL32rr GR32:$src)>; 2458 def : Pat<(and GR64:$src, (add GR64:$src, 1)), 2459 (BLCFILL64rr GR64:$src)>; 2460 2461 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), 2462 (BLCI32rr GR32:$src)>; 2463 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), 2464 (BLCI64rr GR64:$src)>; 2465 2466 // Extra patterns because opt can optimize the above patterns to this. 2467 def : Pat<(or GR32:$src, (sub -2, GR32:$src)), 2468 (BLCI32rr GR32:$src)>; 2469 def : Pat<(or GR64:$src, (sub -2, GR64:$src)), 2470 (BLCI64rr GR64:$src)>; 2471 2472 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), 2473 (BLCIC32rr GR32:$src)>; 2474 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), 2475 (BLCIC64rr GR64:$src)>; 2476 2477 def : Pat<(xor GR32:$src, (add GR32:$src, 1)), 2478 (BLCMSK32rr GR32:$src)>; 2479 def : Pat<(xor GR64:$src, (add GR64:$src, 1)), 2480 (BLCMSK64rr GR64:$src)>; 2481 2482 def : Pat<(or GR32:$src, (add GR32:$src, 1)), 2483 (BLCS32rr GR32:$src)>; 2484 def : Pat<(or GR64:$src, (add GR64:$src, 1)), 2485 (BLCS64rr GR64:$src)>; 2486 2487 def : Pat<(or GR32:$src, (add GR32:$src, -1)), 2488 (BLSFILL32rr GR32:$src)>; 2489 def : Pat<(or GR64:$src, (add GR64:$src, -1)), 2490 (BLSFILL64rr GR64:$src)>; 2491 2492 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), 2493 (BLSIC32rr GR32:$src)>; 2494 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), 2495 (BLSIC64rr GR64:$src)>; 2496 2497 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), 2498 (T1MSKC32rr GR32:$src)>; 2499 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), 2500 (T1MSKC64rr GR64:$src)>; 2501 2502 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), 2503 (TZMSK32rr GR32:$src)>; 2504 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), 2505 (TZMSK64rr GR64:$src)>; 2506 } // HasTBM 2507 2508 //===----------------------------------------------------------------------===// 2509 // Memory Instructions 2510 // 2511 2512 def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), 2513 "clflushopt\t$src", []>, PD; 2514 def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD; 2515 def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD; 2516 2517 2518 //===----------------------------------------------------------------------===// 2519 // Subsystems. 2520 //===----------------------------------------------------------------------===// 2521 2522 include "X86InstrArithmetic.td" 2523 include "X86InstrCMovSetCC.td" 2524 include "X86InstrExtension.td" 2525 include "X86InstrControl.td" 2526 include "X86InstrShiftRotate.td" 2527 2528 // X87 Floating Point Stack. 2529 include "X86InstrFPStack.td" 2530 2531 // SIMD support (SSE, MMX and AVX) 2532 include "X86InstrFragmentsSIMD.td" 2533 2534 // FMA - Fused Multiply-Add support (requires FMA) 2535 include "X86InstrFMA.td" 2536 2537 // XOP 2538 include "X86InstrXOP.td" 2539 2540 // SSE, MMX and 3DNow! vector support. 2541 include "X86InstrSSE.td" 2542 include "X86InstrAVX512.td" 2543 include "X86InstrMMX.td" 2544 include "X86Instr3DNow.td" 2545 2546 // MPX instructions 2547 include "X86InstrMPX.td" 2548 2549 include "X86InstrVMX.td" 2550 include "X86InstrSVM.td" 2551 2552 include "X86InstrTSX.td" 2553 include "X86InstrSGX.td" 2554 2555 // System instructions. 2556 include "X86InstrSystem.td" 2557 2558 // Compiler Pseudo Instructions and Pat Patterns 2559 include "X86InstrCompiler.td" 2560 2561 //===----------------------------------------------------------------------===// 2562 // Assembler Mnemonic Aliases 2563 //===----------------------------------------------------------------------===// 2564 2565 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 2566 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 2567 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 2568 2569 def : MnemonicAlias<"cbw", "cbtw", "att">; 2570 def : MnemonicAlias<"cwde", "cwtl", "att">; 2571 def : MnemonicAlias<"cwd", "cwtd", "att">; 2572 def : MnemonicAlias<"cdq", "cltd", "att">; 2573 def : MnemonicAlias<"cdqe", "cltq", "att">; 2574 def : MnemonicAlias<"cqo", "cqto", "att">; 2575 2576 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 2577 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 2578 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 2579 2580 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 2581 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 2582 2583 def : MnemonicAlias<"loopz", "loope">; 2584 def : MnemonicAlias<"loopnz", "loopne">; 2585 2586 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 2587 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 2588 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 2589 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 2590 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 2591 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 2592 def : MnemonicAlias<"popfd", "popfl", "att">; 2593 2594 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 2595 // all modes. However: "push (addr)" and "push $42" should default to 2596 // pushl/pushq depending on the current mode. Similar for "pop %bx" 2597 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 2598 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 2599 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 2600 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 2601 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 2602 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 2603 def : MnemonicAlias<"pushfd", "pushfl", "att">; 2604 2605 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 2606 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 2607 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 2608 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 2609 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 2610 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 2611 2612 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 2613 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 2614 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 2615 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 2616 2617 def : MnemonicAlias<"repe", "rep">; 2618 def : MnemonicAlias<"repz", "rep">; 2619 def : MnemonicAlias<"repnz", "repne">; 2620 2621 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 2622 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 2623 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 2624 2625 def : MnemonicAlias<"sal", "shl", "intel">; 2626 def : MnemonicAlias<"salb", "shlb", "att">; 2627 def : MnemonicAlias<"salw", "shlw", "att">; 2628 def : MnemonicAlias<"sall", "shll", "att">; 2629 def : MnemonicAlias<"salq", "shlq", "att">; 2630 2631 def : MnemonicAlias<"smovb", "movsb", "att">; 2632 def : MnemonicAlias<"smovw", "movsw", "att">; 2633 def : MnemonicAlias<"smovl", "movsl", "att">; 2634 def : MnemonicAlias<"smovq", "movsq", "att">; 2635 2636 def : MnemonicAlias<"ud2a", "ud2", "att">; 2637 def : MnemonicAlias<"verrw", "verr", "att">; 2638 2639 // System instruction aliases. 2640 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 2641 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 2642 def : MnemonicAlias<"sysret", "sysretl", "att">; 2643 def : MnemonicAlias<"sysexit", "sysexitl", "att">; 2644 2645 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 2646 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 2647 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 2648 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 2649 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 2650 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 2651 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 2652 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 2653 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 2654 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 2655 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 2656 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 2657 2658 2659 // Floating point stack aliases. 2660 def : MnemonicAlias<"fcmovz", "fcmove", "att">; 2661 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 2662 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 2663 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 2664 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 2665 def : MnemonicAlias<"fcomip", "fcompi">; 2666 def : MnemonicAlias<"fildq", "fildll", "att">; 2667 def : MnemonicAlias<"fistpq", "fistpll", "att">; 2668 def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 2669 def : MnemonicAlias<"fldcww", "fldcw", "att">; 2670 def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 2671 def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 2672 def : MnemonicAlias<"fucomip", "fucompi">; 2673 def : MnemonicAlias<"fwait", "wait">; 2674 2675 def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; 2676 def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; 2677 def : MnemonicAlias<"xsaveq", "xsave64", "att">; 2678 def : MnemonicAlias<"xrstorq", "xrstor64", "att">; 2679 def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; 2680 def : MnemonicAlias<"xrstorsq", "xrstors64", "att">; 2681 def : MnemonicAlias<"xsavecq", "xsavec64", "att">; 2682 def : MnemonicAlias<"xsavesq", "xsaves64", "att">; 2683 2684 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 2685 string VariantName> 2686 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 2687 !strconcat(Prefix, NewCond, Suffix), VariantName>; 2688 2689 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 2690 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 2691 /// example "setz" -> "sete". 2692 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 2693 string V = ""> { 2694 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 2695 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 2696 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 2697 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 2698 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 2699 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 2700 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 2701 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 2702 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 2703 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 2704 2705 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 2706 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 2707 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 2708 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 2709 } 2710 2711 // Aliases for set<CC> 2712 defm : IntegerCondCodeMnemonicAlias<"set", "">; 2713 // Aliases for j<CC> 2714 defm : IntegerCondCodeMnemonicAlias<"j", "">; 2715 // Aliases for cmov<CC>{w,l,q} 2716 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 2717 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 2718 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 2719 // No size suffix for intel-style asm. 2720 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 2721 2722 2723 //===----------------------------------------------------------------------===// 2724 // Assembler Instruction Aliases 2725 //===----------------------------------------------------------------------===// 2726 2727 // aad/aam default to base 10 if no operand is specified. 2728 def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>; 2729 def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>; 2730 2731 // Disambiguate the mem/imm form of bt-without-a-suffix as btl. 2732 // Likewise for btc/btr/bts. 2733 def : InstAlias<"bt {$imm, $mem|$mem, $imm}", 2734 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2735 def : InstAlias<"btc {$imm, $mem|$mem, $imm}", 2736 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2737 def : InstAlias<"btr {$imm, $mem|$mem, $imm}", 2738 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2739 def : InstAlias<"bts {$imm, $mem|$mem, $imm}", 2740 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2741 2742 // clr aliases. 2743 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 2744 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 2745 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 2746 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 2747 2748 // lods aliases. Accept the destination being omitted because it's implicit 2749 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2750 // in the destination. 2751 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>; 2752 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>; 2753 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>; 2754 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2755 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 2756 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 2757 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 2758 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2759 2760 // stos aliases. Accept the source being omitted because it's implicit in 2761 // the mnemonic, or the mnemonic suffix being omitted because it's implicit 2762 // in the source. 2763 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>; 2764 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>; 2765 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>; 2766 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2767 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 2768 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 2769 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 2770 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2771 2772 // scas aliases. Accept the destination being omitted because it's implicit 2773 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2774 // in the destination. 2775 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>; 2776 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>; 2777 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>; 2778 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2779 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 2780 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 2781 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 2782 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2783 2784 // div and idiv aliases for explicit A register. 2785 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 2786 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 2787 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 2788 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 2789 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 2790 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 2791 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 2792 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 2793 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 2794 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 2795 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 2796 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 2797 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 2798 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 2799 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 2800 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 2801 2802 2803 2804 // Various unary fpstack operations default to operating on on ST1. 2805 // For example, "fxch" -> "fxch %st(1)" 2806 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 2807 def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; 2808 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 2809 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 2810 def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; 2811 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 2812 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 2813 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 2814 def : InstAlias<"fxch", (XCH_F ST1), 0>; 2815 def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 2816 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 2817 def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 2818 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 2819 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 2820 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 2821 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 2822 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 2823 2824 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 2825 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 2826 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 2827 // gas. 2828 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 2829 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"), 2830 (Inst RST:$op), EmitAlias>; 2831 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"), 2832 (Inst ST0), EmitAlias>; 2833 } 2834 2835 defm : FpUnaryAlias<"fadd", ADD_FST0r>; 2836 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 2837 defm : FpUnaryAlias<"fsub", SUB_FST0r>; 2838 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; 2839 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; 2840 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; 2841 defm : FpUnaryAlias<"fmul", MUL_FST0r>; 2842 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; 2843 defm : FpUnaryAlias<"fdiv", DIV_FST0r>; 2844 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; 2845 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; 2846 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; 2847 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 2848 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 2849 defm : FpUnaryAlias<"fcompi", COM_FIPr>; 2850 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; 2851 2852 2853 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they 2854 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 2855 // solely because gas supports it. 2856 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; 2857 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; 2858 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; 2859 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; 2860 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; 2861 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; 2862 2863 // We accept "fnstsw %eax" even though it only writes %ax. 2864 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>; 2865 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>; 2866 def : InstAlias<"fnstsw" , (FNSTSW16r)>; 2867 2868 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 2869 // this is compatible with what GAS does. 2870 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2871 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2872 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2873 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2874 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2875 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2876 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2877 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2878 2879 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>; 2880 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>; 2881 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>; 2882 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>; 2883 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2884 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2885 2886 2887 // "imul <imm>, B" is an alias for "imul <imm>, B, B". 2888 def : InstAlias<"imul{w} {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; 2889 def : InstAlias<"imul{w} {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; 2890 def : InstAlias<"imul{l} {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; 2891 def : InstAlias<"imul{l} {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; 2892 def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; 2893 def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; 2894 2895 // inb %dx -> inb %al, %dx 2896 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 2897 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 2898 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 2899 def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>; 2900 def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>; 2901 def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>; 2902 2903 2904 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 2905 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2906 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2907 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2908 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2909 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>; 2910 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>; 2911 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 2912 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 2913 2914 // Force mov without a suffix with a segment and mem to prefer the 'l' form of 2915 // the move. All segment/mem forms are equivalent, this has the shortest 2916 // encoding. 2917 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>; 2918 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>; 2919 2920 // Match 'movq <largeimm>, <reg>' as an alias for movabsq. 2921 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 2922 2923 // Match 'movq GR64, MMX' as an alias for movd. 2924 def : InstAlias<"movq {$src, $dst|$dst, $src}", 2925 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 2926 def : InstAlias<"movq {$src, $dst|$dst, $src}", 2927 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 2928 2929 // movsx aliases 2930 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; 2931 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; 2932 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; 2933 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; 2934 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; 2935 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; 2936 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; 2937 2938 // movzx aliases 2939 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; 2940 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; 2941 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; 2942 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; 2943 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; 2944 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; 2945 // Note: No GR32->GR64 movzx form. 2946 2947 // outb %dx -> outb %al, %dx 2948 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 2949 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 2950 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 2951 def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>; 2952 def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>; 2953 def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>; 2954 2955 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 2956 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 2957 // errors, since its encoding is the most compact. 2958 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 2959 2960 // shld/shrd op,op -> shld op, op, CL 2961 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 2962 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 2963 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 2964 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 2965 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 2966 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 2967 2968 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 2969 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 2970 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 2971 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 2972 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 2973 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 2974 2975 /* FIXME: This is disabled because the asm matcher is currently incapable of 2976 * matching a fixed immediate like $1. 2977 // "shl X, $1" is an alias for "shl X". 2978 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 2979 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2980 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 2981 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2982 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 2983 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2984 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 2985 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2986 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 2987 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2988 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 2989 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2990 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 2991 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2992 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 2993 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2994 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 2995 } 2996 2997 defm : ShiftRotateByOneAlias<"rcl", "RCL">; 2998 defm : ShiftRotateByOneAlias<"rcr", "RCR">; 2999 defm : ShiftRotateByOneAlias<"rol", "ROL">; 3000 defm : ShiftRotateByOneAlias<"ror", "ROR">; 3001 FIXME */ 3002 3003 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 3004 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", 3005 (TEST8rm GR8 :$val, i8mem :$mem), 0>; 3006 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", 3007 (TEST16rm GR16:$val, i16mem:$mem), 0>; 3008 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", 3009 (TEST32rm GR32:$val, i32mem:$mem), 0>; 3010 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", 3011 (TEST64rm GR64:$val, i64mem:$mem), 0>; 3012 3013 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 3014 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 3015 (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 3016 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 3017 (XCHG16rm GR16:$val, i16mem:$mem), 0>; 3018 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 3019 (XCHG32rm GR32:$val, i32mem:$mem), 0>; 3020 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 3021 (XCHG64rm GR64:$val, i64mem:$mem), 0>; 3022 3023 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 3024 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 3025 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 3026 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>; 3027 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 3028 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>; 3029 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 3030 3031 // These aliases exist to get the parser to prioritize matching 8-bit 3032 // immediate encodings over matching the implicit ax/eax/rax encodings. By 3033 // explicitly mentioning the A register here, these entries will be ordered 3034 // first due to the more explicit immediate type. 3035 def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; 3036 def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; 3037 def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; 3038 def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; 3039 def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; 3040 def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; 3041 def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; 3042 def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>; 3043 3044 def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>; 3045 def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>; 3046 def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>; 3047 def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>; 3048 def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>; 3049 def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>; 3050 def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>; 3051 def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>; 3052 3053 def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>; 3054 def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>; 3055 def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>; 3056 def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>; 3057 def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>; 3058 def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>; 3059 def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>; 3060 def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>; 3061
