1 ; RUN: llc -aarch64-extr-generation=true -verify-machineinstrs < %s \ 2 ; RUN: -march=arm64 | FileCheck %s 3 4 define i64 @ror_i64(i64 %in) { 5 ; CHECK-LABEL: ror_i64: 6 %left = shl i64 %in, 19 7 %right = lshr i64 %in, 45 8 %val5 = or i64 %left, %right 9 ; CHECK: ror {{x[0-9]+}}, x0, #45 10 ret i64 %val5 11 } 12 13 define i32 @ror_i32(i32 %in) { 14 ; CHECK-LABEL: ror_i32: 15 %left = shl i32 %in, 9 16 %right = lshr i32 %in, 23 17 %val5 = or i32 %left, %right 18 ; CHECK: ror {{w[0-9]+}}, w0, #23 19 ret i32 %val5 20 } 21 22 define i32 @extr_i32(i32 %lhs, i32 %rhs) { 23 ; CHECK-LABEL: extr_i32: 24 %left = shl i32 %lhs, 6 25 %right = lshr i32 %rhs, 26 26 %val = or i32 %left, %right 27 ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use 28 ; something other than w0 and w1. 29 ; CHECK: extr {{w[0-9]+}}, w0, w1, #26 30 31 ret i32 %val 32 } 33 34 define i64 @extr_i64(i64 %lhs, i64 %rhs) { 35 ; CHECK-LABEL: extr_i64: 36 %right = lshr i64 %rhs, 40 37 %left = shl i64 %lhs, 24 38 %val = or i64 %right, %left 39 ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use 40 ; something other than w0 and w1. 41 ; CHECK: extr {{x[0-9]+}}, x0, x1, #40 42 43 ret i64 %val 44 } 45 46 ; Regression test: a bad experimental pattern crept into git which optimised 47 ; this pattern to a single EXTR. 48 define i32 @extr_regress(i32 %a, i32 %b) { 49 ; CHECK-LABEL: extr_regress: 50 51 %sh1 = shl i32 %a, 14 52 %sh2 = lshr i32 %b, 14 53 %val = or i32 %sh2, %sh1 54 ; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}} 55 56 ret i32 %val 57 ; CHECK: ret 58 } 59
