1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s 2 3 define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind { 4 ; CHECK-LABEL: v_orrimm: 5 ; CHECK-NOT: mov 6 ; CHECK-NOT: mvn 7 ; CHECK: orr 8 %tmp1 = load <8 x i8>, <8 x i8>* %A 9 %tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1> 10 ret <8 x i8> %tmp3 11 } 12 13 define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind { 14 ; CHECK: v_orrimmQ 15 ; CHECK-NOT: mov 16 ; CHECK-NOT: mvn 17 ; CHECK: orr 18 %tmp1 = load <16 x i8>, <16 x i8>* %A 19 %tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1> 20 ret <16 x i8> %tmp3 21 } 22 23 define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { 24 ; CHECK-LABEL: v_bicimm: 25 ; CHECK-NOT: mov 26 ; CHECK-NOT: mvn 27 ; CHECK: bic 28 %tmp1 = load <8 x i8>, <8 x i8>* %A 29 %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > 30 ret <8 x i8> %tmp3 31 } 32 33 define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { 34 ; CHECK-LABEL: v_bicimmQ: 35 ; CHECK-NOT: mov 36 ; CHECK-NOT: mvn 37 ; CHECK: bic 38 %tmp1 = load <16 x i8>, <16 x i8>* %A 39 %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > 40 ret <16 x i8> %tmp3 41 } 42 43 define <2 x double> @foo(<2 x double> %bar) nounwind { 44 ; CHECK: foo 45 ; CHECK: fmov.2d v1, #1.0000000 46 %add = fadd <2 x double> %bar, <double 1.0, double 1.0> 47 ret <2 x double> %add 48 } 49 50 define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp { 51 entry: 52 ; CHECK-LABEL: movi_4s_imm_t1: 53 ; CHECK: movi.4s v0, #0x4b 54 ret <4 x i32> <i32 75, i32 75, i32 75, i32 75> 55 } 56 57 define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp { 58 entry: 59 ; CHECK-LABEL: movi_4s_imm_t2: 60 ; CHECK: movi.4s v0, #0x4b, lsl #8 61 ret <4 x i32> <i32 19200, i32 19200, i32 19200, i32 19200> 62 } 63 64 define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp { 65 entry: 66 ; CHECK-LABEL: movi_4s_imm_t3: 67 ; CHECK: movi.4s v0, #0x4b, lsl #16 68 ret <4 x i32> <i32 4915200, i32 4915200, i32 4915200, i32 4915200> 69 } 70 71 define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp { 72 entry: 73 ; CHECK-LABEL: movi_4s_imm_t4: 74 ; CHECK: movi.4s v0, #0x4b, lsl #24 75 ret <4 x i32> <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200> 76 } 77 78 define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp { 79 entry: 80 ; CHECK-LABEL: movi_8h_imm_t5: 81 ; CHECK: movi.8h v0, #0x4b 82 ret <8 x i16> <i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75> 83 } 84 85 ; rdar://11989841 86 define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp { 87 entry: 88 ; CHECK-LABEL: movi_8h_imm_t6: 89 ; CHECK: movi.8h v0, #0x4b, lsl #8 90 ret <8 x i16> <i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200> 91 } 92 93 define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp { 94 entry: 95 ; CHECK-LABEL: movi_4s_imm_t7: 96 ; CHECK: movi.4s v0, #0x4b, msl #8 97 ret <4 x i32> <i32 19455, i32 19455, i32 19455, i32 19455> 98 } 99 100 define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp { 101 entry: 102 ; CHECK-LABEL: movi_4s_imm_t8: 103 ; CHECK: movi.4s v0, #0x4b, msl #16 104 ret <4 x i32> <i32 4980735, i32 4980735, i32 4980735, i32 4980735> 105 } 106 107 define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp { 108 entry: 109 ; CHECK-LABEL: movi_16b_imm_t9: 110 ; CHECK: movi.16b v0, #0x4b 111 ret <16 x i8> <i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, 112 i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75> 113 } 114 115 define <2 x i64> @movi_2d_imm_t10() nounwind readnone ssp { 116 entry: 117 ; CHECK-LABEL: movi_2d_imm_t10: 118 ; CHECK: movi.2d v0, #0xff00ff00ff00ff 119 ret <2 x i64> <i64 71777214294589695, i64 71777214294589695> 120 } 121 122 define <4 x i32> @movi_4s_imm_t11() nounwind readnone ssp { 123 entry: 124 ; CHECK-LABEL: movi_4s_imm_t11: 125 ; CHECK: fmov.4s v0, #-0.32812500 126 ret <4 x i32> <i32 3198681088, i32 3198681088, i32 3198681088, i32 3198681088> 127 } 128 129 define <2 x i64> @movi_2d_imm_t12() nounwind readnone ssp { 130 entry: 131 ; CHECK-LABEL: movi_2d_imm_t12: 132 ; CHECK: fmov.2d v0, #-0.17187500 133 ret <2 x i64> <i64 13818732506632945664, i64 13818732506632945664> 134 } 135
