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      1 ; RUN: llc -mtriple=arm64-linux-gnu -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s
      2 ; RUN: llc -mtriple=arm64-linux-gnu -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s
      3 
      4 define i32 @test1(i32 %x) {
      5 ; CHECK-LABEL: test1
      6 ; CHECK: add w8, w0, #7
      7 ; CHECK: cmp w0, #0
      8 ; CHECK: csel w8, w8, w0, lt
      9 ; CHECK: asr w0, w8, #3
     10   %div = sdiv i32 %x, 8
     11   ret i32 %div
     12 }
     13 
     14 define i32 @test2(i32 %x) {
     15 ; CHECK-LABEL: test2
     16 ; CHECK: add w8, w0, #7
     17 ; CHECK: cmp w0, #0
     18 ; CHECK: csel w8, w8, w0, lt
     19 ; CHECK: neg w0, w8, asr #3
     20   %div = sdiv i32 %x, -8
     21   ret i32 %div
     22 }
     23 
     24 define i32 @test3(i32 %x) {
     25 ; CHECK-LABEL: test3
     26 ; CHECK: add w8, w0, #31
     27 ; CHECK: cmp w0, #0
     28 ; CHECK: csel w8, w8, w0, lt
     29 ; CHECK: asr w0, w8, #5
     30   %div = sdiv i32 %x, 32
     31   ret i32 %div
     32 }
     33 
     34 define i64 @test4(i64 %x) {
     35 ; CHECK-LABEL: test4
     36 ; CHECK: add x8, x0, #7
     37 ; CHECK: cmp x0, #0
     38 ; CHECK: csel x8, x8, x0, lt
     39 ; CHECK: asr x0, x8, #3
     40   %div = sdiv i64 %x, 8
     41   ret i64 %div
     42 }
     43 
     44 define i64 @test5(i64 %x) {
     45 ; CHECK-LABEL: test5
     46 ; CHECK: add x8, x0, #7
     47 ; CHECK: cmp x0, #0
     48 ; CHECK: csel x8, x8, x0, lt
     49 ; CHECK: neg x0, x8, asr #3
     50   %div = sdiv i64 %x, -8
     51   ret i64 %div
     52 }
     53 
     54 define i64 @test6(i64 %x) {
     55 ; CHECK-LABEL: test6
     56 ; CHECK: add x8, x0, #63
     57 ; CHECK: cmp x0, #0
     58 ; CHECK: csel x8, x8, x0, lt
     59 ; CHECK: asr x0, x8, #6
     60   %div = sdiv i64 %x, 64
     61   ret i64 %div
     62 }
     63 
     64 define i64 @test7(i64 %x) {
     65 ; CHECK-LABEL: test7
     66 ; CHECK: orr [[REG:x[0-9]+]], xzr, #0xffffffffffff
     67 ; CHECK: add x8, x0, [[REG]]
     68 ; CHECK: cmp x0, #0
     69 ; CHECK: csel x8, x8, x0, lt
     70 ; CHECK: asr x0, x8, #48
     71   %div = sdiv i64 %x, 281474976710656
     72   ret i64 %div
     73 }
     74 
     75