1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 2 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI 3 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI 4 5 ; R600: {{^}}build_vector2: 6 ; R600: MOV 7 ; R600: MOV 8 ; R600-NOT: MOV 9 ; SI: {{^}}build_vector2: 10 ; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 11 ; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 12 ; SI: buffer_store_dwordx2 v{{\[}}[[X]]:[[Y]]{{\]}} 13 define void @build_vector2 (<2 x i32> addrspace(1)* %out) { 14 entry: 15 store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out 16 ret void 17 } 18 19 ; R600: {{^}}build_vector4: 20 ; R600: MOV 21 ; R600: MOV 22 ; R600: MOV 23 ; R600: MOV 24 ; R600-NOT: MOV 25 ; SI: {{^}}build_vector4: 26 ; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 27 ; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 28 ; SI-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7 29 ; SI-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8 30 ; SI: buffer_store_dwordx4 v{{\[}}[[X]]:[[W]]{{\]}} 31 define void @build_vector4 (<4 x i32> addrspace(1)* %out) { 32 entry: 33 store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out 34 ret void 35 } 36
