1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=CHECK %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CHECK %s 3 4 ; Use a 64-bit value with lo bits that can be represented as an inline constant 5 ; CHECK-LABEL: {{^}}i64_imm_inline_lo: 6 ; CHECK: v_mov_b32_e32 v[[LO_VGPR:[0-9]+]], 5 7 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VGPR]]: 8 define void @i64_imm_inline_lo(i64 addrspace(1) *%out) { 9 entry: 10 store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005 11 ret void 12 } 13 14 ; Use a 64-bit value with hi bits that can be represented as an inline constant 15 ; CHECK-LABEL: {{^}}i64_imm_inline_hi: 16 ; CHECK: v_mov_b32_e32 v[[HI_VGPR:[0-9]+]], 5 17 ; CHECK: buffer_store_dwordx2 v{{\[[0-9]+:}}[[HI_VGPR]] 18 define void @i64_imm_inline_hi(i64 addrspace(1) *%out) { 19 entry: 20 store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678 21 ret void 22 } 23 24 ; CHECK-LABEL: {{^}}store_imm_neg_0.0_i64: 25 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 26 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x80000000 27 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 28 define void @store_imm_neg_0.0_i64(i64 addrspace(1) *%out) { 29 store i64 -9223372036854775808, i64 addrspace(1) *%out 30 ret void 31 } 32 33 ; CHECK-LABEL: {{^}}store_inline_imm_neg_0.0_i32: 34 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 35 ; CHECK: buffer_store_dword [[REG]] 36 define void @store_inline_imm_neg_0.0_i32(i32 addrspace(1)* %out) { 37 store i32 -2147483648, i32 addrspace(1)* %out 38 ret void 39 } 40 41 ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32: 42 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} 43 ; CHECK: buffer_store_dword [[REG]] 44 define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) { 45 store float 0.0, float addrspace(1)* %out 46 ret void 47 } 48 49 ; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32: 50 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 51 ; CHECK: buffer_store_dword [[REG]] 52 define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) { 53 store float -0.0, float addrspace(1)* %out 54 ret void 55 } 56 57 ; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32: 58 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}} 59 ; CHECK: buffer_store_dword [[REG]] 60 define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) { 61 store float 0.5, float addrspace(1)* %out 62 ret void 63 } 64 65 ; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32: 66 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}} 67 ; CHECK: buffer_store_dword [[REG]] 68 define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) { 69 store float -0.5, float addrspace(1)* %out 70 ret void 71 } 72 73 ; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32: 74 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}} 75 ; CHECK: buffer_store_dword [[REG]] 76 define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) { 77 store float 1.0, float addrspace(1)* %out 78 ret void 79 } 80 81 ; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32: 82 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}} 83 ; CHECK: buffer_store_dword [[REG]] 84 define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) { 85 store float -1.0, float addrspace(1)* %out 86 ret void 87 } 88 89 ; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32: 90 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}} 91 ; CHECK: buffer_store_dword [[REG]] 92 define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) { 93 store float 2.0, float addrspace(1)* %out 94 ret void 95 } 96 97 ; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32: 98 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}} 99 ; CHECK: buffer_store_dword [[REG]] 100 define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) { 101 store float -2.0, float addrspace(1)* %out 102 ret void 103 } 104 105 ; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32: 106 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}} 107 ; CHECK: buffer_store_dword [[REG]] 108 define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) { 109 store float 4.0, float addrspace(1)* %out 110 ret void 111 } 112 113 ; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32: 114 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}} 115 ; CHECK: buffer_store_dword [[REG]] 116 define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) { 117 store float -4.0, float addrspace(1)* %out 118 ret void 119 } 120 121 ; CHECK-LABEL: {{^}}store_literal_imm_f32: 122 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000 123 ; CHECK: buffer_store_dword [[REG]] 124 define void @store_literal_imm_f32(float addrspace(1)* %out) { 125 store float 4096.0, float addrspace(1)* %out 126 ret void 127 } 128 129 ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32: 130 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 131 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}} 132 ; CHECK: buffer_store_dword [[REG]] 133 define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) { 134 %y = fadd float %x, 0.0 135 store float %y, float addrspace(1)* %out 136 ret void 137 } 138 139 ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32: 140 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 141 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}} 142 ; CHECK: buffer_store_dword [[REG]] 143 define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) { 144 %y = fadd float %x, 0.5 145 store float %y, float addrspace(1)* %out 146 ret void 147 } 148 149 ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32: 150 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 151 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}} 152 ; CHECK: buffer_store_dword [[REG]] 153 define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) { 154 %y = fadd float %x, -0.5 155 store float %y, float addrspace(1)* %out 156 ret void 157 } 158 159 ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32: 160 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 161 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}} 162 ; CHECK: buffer_store_dword [[REG]] 163 define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) { 164 %y = fadd float %x, 1.0 165 store float %y, float addrspace(1)* %out 166 ret void 167 } 168 169 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32: 170 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 171 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}} 172 ; CHECK: buffer_store_dword [[REG]] 173 define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) { 174 %y = fadd float %x, -1.0 175 store float %y, float addrspace(1)* %out 176 ret void 177 } 178 179 ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32: 180 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 181 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}} 182 ; CHECK: buffer_store_dword [[REG]] 183 define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) { 184 %y = fadd float %x, 2.0 185 store float %y, float addrspace(1)* %out 186 ret void 187 } 188 189 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32: 190 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 191 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}} 192 ; CHECK: buffer_store_dword [[REG]] 193 define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) { 194 %y = fadd float %x, -2.0 195 store float %y, float addrspace(1)* %out 196 ret void 197 } 198 199 ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32: 200 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 201 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}} 202 ; CHECK: buffer_store_dword [[REG]] 203 define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) { 204 %y = fadd float %x, 4.0 205 store float %y, float addrspace(1)* %out 206 ret void 207 } 208 209 ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32: 210 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 211 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}} 212 ; CHECK: buffer_store_dword [[REG]] 213 define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) { 214 %y = fadd float %x, -4.0 215 store float %y, float addrspace(1)* %out 216 ret void 217 } 218 219 ; CHECK-LABEL: {{^}}commute_add_inline_imm_0.5_f32: 220 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]] 221 ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]] 222 ; CHECK: buffer_store_dword [[REG]] 223 define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addrspace(1)* %in) { 224 %x = load float, float addrspace(1)* %in 225 %y = fadd float %x, 0.5 226 store float %y, float addrspace(1)* %out 227 ret void 228 } 229 230 ; CHECK-LABEL: {{^}}commute_add_literal_f32: 231 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]] 232 ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]] 233 ; CHECK: buffer_store_dword [[REG]] 234 define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1)* %in) { 235 %x = load float, float addrspace(1)* %in 236 %y = fadd float %x, 1024.0 237 store float %y, float addrspace(1)* %out 238 ret void 239 } 240 241 ; CHECK-LABEL: {{^}}add_inline_imm_1_f32: 242 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 243 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}} 244 ; CHECK: buffer_store_dword [[REG]] 245 define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) { 246 %y = fadd float %x, 0x36a0000000000000 247 store float %y, float addrspace(1)* %out 248 ret void 249 } 250 251 ; CHECK-LABEL: {{^}}add_inline_imm_2_f32: 252 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 253 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2, [[VAL]]{{$}} 254 ; CHECK: buffer_store_dword [[REG]] 255 define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) { 256 %y = fadd float %x, 0x36b0000000000000 257 store float %y, float addrspace(1)* %out 258 ret void 259 } 260 261 ; CHECK-LABEL: {{^}}add_inline_imm_16_f32: 262 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 263 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 16, [[VAL]] 264 ; CHECK: buffer_store_dword [[REG]] 265 define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) { 266 %y = fadd float %x, 0x36e0000000000000 267 store float %y, float addrspace(1)* %out 268 ret void 269 } 270 271 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32: 272 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 273 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1, [[VAL]] 274 ; CHECK: buffer_store_dword [[REG]] 275 define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) { 276 %y = fadd float %x, 0xffffffffe0000000 277 store float %y, float addrspace(1)* %out 278 ret void 279 } 280 281 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32: 282 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 283 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2, [[VAL]] 284 ; CHECK: buffer_store_dword [[REG]] 285 define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) { 286 %y = fadd float %x, 0xffffffffc0000000 287 store float %y, float addrspace(1)* %out 288 ret void 289 } 290 291 ; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32: 292 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 293 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -16, [[VAL]] 294 ; CHECK: buffer_store_dword [[REG]] 295 define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) { 296 %y = fadd float %x, 0xfffffffe00000000 297 store float %y, float addrspace(1)* %out 298 ret void 299 } 300 301 ; CHECK-LABEL: {{^}}add_inline_imm_63_f32: 302 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 303 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 63, [[VAL]] 304 ; CHECK: buffer_store_dword [[REG]] 305 define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) { 306 %y = fadd float %x, 0x36ff800000000000 307 store float %y, float addrspace(1)* %out 308 ret void 309 } 310 311 ; CHECK-LABEL: {{^}}add_inline_imm_64_f32: 312 ; CHECK: s_load_dword [[VAL:s[0-9]+]] 313 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 64, [[VAL]] 314 ; CHECK: buffer_store_dword [[REG]] 315 define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) { 316 %y = fadd float %x, 0x3700000000000000 317 store float %y, float addrspace(1)* %out 318 ret void 319 } 320 321 322 ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f64: 323 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 324 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 325 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0, [[VAL]] 326 ; CHECK: buffer_store_dwordx2 [[REG]] 327 define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) { 328 %y = fadd double %x, 0.0 329 store double %y, double addrspace(1)* %out 330 ret void 331 } 332 333 ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f64: 334 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 335 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 336 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0.5, [[VAL]] 337 ; CHECK: buffer_store_dwordx2 [[REG]] 338 define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) { 339 %y = fadd double %x, 0.5 340 store double %y, double addrspace(1)* %out 341 ret void 342 } 343 344 ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f64: 345 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 346 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 347 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -0.5, [[VAL]] 348 ; CHECK: buffer_store_dwordx2 [[REG]] 349 define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) { 350 %y = fadd double %x, -0.5 351 store double %y, double addrspace(1)* %out 352 ret void 353 } 354 355 ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f64: 356 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 357 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 358 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1.0, [[VAL]] 359 ; CHECK: buffer_store_dwordx2 [[REG]] 360 define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) { 361 %y = fadd double %x, 1.0 362 store double %y, double addrspace(1)* %out 363 ret void 364 } 365 366 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f64: 367 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 368 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 369 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1.0, [[VAL]] 370 ; CHECK: buffer_store_dwordx2 [[REG]] 371 define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) { 372 %y = fadd double %x, -1.0 373 store double %y, double addrspace(1)* %out 374 ret void 375 } 376 377 ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f64: 378 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 379 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 380 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2.0, [[VAL]] 381 ; CHECK: buffer_store_dwordx2 [[REG]] 382 define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) { 383 %y = fadd double %x, 2.0 384 store double %y, double addrspace(1)* %out 385 ret void 386 } 387 388 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f64: 389 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 390 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 391 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2.0, [[VAL]] 392 ; CHECK: buffer_store_dwordx2 [[REG]] 393 define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) { 394 %y = fadd double %x, -2.0 395 store double %y, double addrspace(1)* %out 396 ret void 397 } 398 399 ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f64: 400 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 401 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 402 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 4.0, [[VAL]] 403 ; CHECK: buffer_store_dwordx2 [[REG]] 404 define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) { 405 %y = fadd double %x, 4.0 406 store double %y, double addrspace(1)* %out 407 ret void 408 } 409 410 ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f64: 411 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 412 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 413 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -4.0, [[VAL]] 414 ; CHECK: buffer_store_dwordx2 [[REG]] 415 define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) { 416 %y = fadd double %x, -4.0 417 store double %y, double addrspace(1)* %out 418 ret void 419 } 420 421 422 ; CHECK-LABEL: {{^}}add_inline_imm_1_f64: 423 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 424 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 425 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1, [[VAL]] 426 ; CHECK: buffer_store_dwordx2 [[REG]] 427 define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) { 428 %y = fadd double %x, 0x0000000000000001 429 store double %y, double addrspace(1)* %out 430 ret void 431 } 432 433 ; CHECK-LABEL: {{^}}add_inline_imm_2_f64: 434 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 435 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 436 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2, [[VAL]] 437 ; CHECK: buffer_store_dwordx2 [[REG]] 438 define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) { 439 %y = fadd double %x, 0x0000000000000002 440 store double %y, double addrspace(1)* %out 441 ret void 442 } 443 444 ; CHECK-LABEL: {{^}}add_inline_imm_16_f64: 445 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 446 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 447 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 16, [[VAL]] 448 ; CHECK: buffer_store_dwordx2 [[REG]] 449 define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) { 450 %y = fadd double %x, 0x0000000000000010 451 store double %y, double addrspace(1)* %out 452 ret void 453 } 454 455 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f64: 456 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 457 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 458 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1, [[VAL]] 459 ; CHECK: buffer_store_dwordx2 [[REG]] 460 define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) { 461 %y = fadd double %x, 0xffffffffffffffff 462 store double %y, double addrspace(1)* %out 463 ret void 464 } 465 466 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f64: 467 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 468 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 469 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2, [[VAL]] 470 ; CHECK: buffer_store_dwordx2 [[REG]] 471 define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) { 472 %y = fadd double %x, 0xfffffffffffffffe 473 store double %y, double addrspace(1)* %out 474 ret void 475 } 476 477 ; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f64: 478 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 479 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 480 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -16, [[VAL]] 481 ; CHECK: buffer_store_dwordx2 [[REG]] 482 define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) { 483 %y = fadd double %x, 0xfffffffffffffff0 484 store double %y, double addrspace(1)* %out 485 ret void 486 } 487 488 ; CHECK-LABEL: {{^}}add_inline_imm_63_f64: 489 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 490 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 491 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 63, [[VAL]] 492 ; CHECK: buffer_store_dwordx2 [[REG]] 493 define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) { 494 %y = fadd double %x, 0x000000000000003F 495 store double %y, double addrspace(1)* %out 496 ret void 497 } 498 499 ; CHECK-LABEL: {{^}}add_inline_imm_64_f64: 500 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 501 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 502 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 64, [[VAL]] 503 ; CHECK: buffer_store_dwordx2 [[REG]] 504 define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) { 505 %y = fadd double %x, 0x0000000000000040 506 store double %y, double addrspace(1)* %out 507 ret void 508 } 509 510 511 ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64: 512 ; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0 513 ; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0 514 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 515 define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) { 516 store double 0.0, double addrspace(1)* %out 517 ret void 518 } 519 520 521 ; CHECK-LABEL: {{^}}store_literal_imm_neg_0.0_f64: 522 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 523 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x80000000 524 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 525 define void @store_literal_imm_neg_0.0_f64(double addrspace(1)* %out) { 526 store double -0.0, double addrspace(1)* %out 527 ret void 528 } 529 530 ; CHECK-LABEL: {{^}}store_inline_imm_0.5_f64: 531 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 532 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3fe00000 533 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 534 define void @store_inline_imm_0.5_f64(double addrspace(1)* %out) { 535 store double 0.5, double addrspace(1)* %out 536 ret void 537 } 538 539 ; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f64: 540 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 541 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbfe00000 542 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 543 define void @store_inline_imm_m_0.5_f64(double addrspace(1)* %out) { 544 store double -0.5, double addrspace(1)* %out 545 ret void 546 } 547 548 ; CHECK-LABEL: {{^}}store_inline_imm_1.0_f64: 549 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 550 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3ff00000 551 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 552 define void @store_inline_imm_1.0_f64(double addrspace(1)* %out) { 553 store double 1.0, double addrspace(1)* %out 554 ret void 555 } 556 557 ; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f64: 558 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 559 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbff00000 560 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 561 define void @store_inline_imm_m_1.0_f64(double addrspace(1)* %out) { 562 store double -1.0, double addrspace(1)* %out 563 ret void 564 } 565 566 ; CHECK-LABEL: {{^}}store_inline_imm_2.0_f64: 567 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 568 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 2.0 569 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 570 define void @store_inline_imm_2.0_f64(double addrspace(1)* %out) { 571 store double 2.0, double addrspace(1)* %out 572 ret void 573 } 574 575 ; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f64: 576 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 577 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], -2.0 578 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 579 define void @store_inline_imm_m_2.0_f64(double addrspace(1)* %out) { 580 store double -2.0, double addrspace(1)* %out 581 ret void 582 } 583 584 ; CHECK-LABEL: {{^}}store_inline_imm_4.0_f64: 585 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 586 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x40100000 587 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 588 define void @store_inline_imm_4.0_f64(double addrspace(1)* %out) { 589 store double 4.0, double addrspace(1)* %out 590 ret void 591 } 592 593 ; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f64: 594 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 595 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xc0100000 596 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 597 define void @store_inline_imm_m_4.0_f64(double addrspace(1)* %out) { 598 store double -4.0, double addrspace(1)* %out 599 ret void 600 } 601 602 ; CHECK-LABEL: {{^}}store_literal_imm_f64: 603 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 604 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x40b00000 605 ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 606 define void @store_literal_imm_f64(double addrspace(1)* %out) { 607 store double 4096.0, double addrspace(1)* %out 608 ret void 609 } 610
