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      1 ; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI %s
      2 ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s
      3 
      4 declare float @llvm.AMDGPU.cvt.f32.ubyte0(i32) nounwind readnone
      5 declare float @llvm.AMDGPU.cvt.f32.ubyte1(i32) nounwind readnone
      6 declare float @llvm.AMDGPU.cvt.f32.ubyte2(i32) nounwind readnone
      7 declare float @llvm.AMDGPU.cvt.f32.ubyte3(i32) nounwind readnone
      8 
      9 ; SI-LABEL: {{^}}test_unpack_byte0_to_float:
     10 ; SI: v_cvt_f32_ubyte0
     11 define void @test_unpack_byte0_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
     12   %val = load i32, i32 addrspace(1)* %in, align 4
     13   %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte0(i32 %val) nounwind readnone
     14   store float %cvt, float addrspace(1)* %out, align 4
     15   ret void
     16 }
     17 
     18 ; SI-LABEL: {{^}}test_unpack_byte1_to_float:
     19 ; SI: v_cvt_f32_ubyte1
     20 define void @test_unpack_byte1_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
     21   %val = load i32, i32 addrspace(1)* %in, align 4
     22   %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %val) nounwind readnone
     23   store float %cvt, float addrspace(1)* %out, align 4
     24   ret void
     25 }
     26 
     27 ; SI-LABEL: {{^}}test_unpack_byte2_to_float:
     28 ; SI: v_cvt_f32_ubyte2
     29 define void @test_unpack_byte2_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
     30   %val = load i32, i32 addrspace(1)* %in, align 4
     31   %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte2(i32 %val) nounwind readnone
     32   store float %cvt, float addrspace(1)* %out, align 4
     33   ret void
     34 }
     35 
     36 ; SI-LABEL: {{^}}test_unpack_byte3_to_float:
     37 ; SI: v_cvt_f32_ubyte3
     38 define void @test_unpack_byte3_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
     39   %val = load i32, i32 addrspace(1)* %in, align 4
     40   %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte3(i32 %val) nounwind readnone
     41   store float %cvt, float addrspace(1)* %out, align 4
     42   ret void
     43 }
     44