1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s 2 ;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s 3 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s 4 5 ;GCN-LABEL: {{^}}main: 6 ;GCN-NOT: s_wqm 7 ;GCN: s_mov_b32 8 ;GCN-NEXT: v_interp_mov_f32 9 ;GCN: v_interp_p1_f32 10 ;GCN: v_interp_p2_f32 11 12 define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 { 13 main_body: 14 %5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3) 15 %6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4) 16 %7 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %4) 17 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %6, float %7, float %7) 18 ret void 19 } 20 21 ; Thest that v_interp_p1 uses different source and destination registers 22 ; on 16 bank LDS chips. 23 24 ; 16BANK-LABEL: {{^}}v_interp_p1_bank16_bug: 25 ; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]] 26 27 define void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { 28 main_body: 29 %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) 30 %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) 31 %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) 32 %25 = call float @fabs(float %22) 33 %26 = call float @fabs(float %23) 34 %27 = call float @fabs(float %24) 35 %28 = call i32 @llvm.SI.packf16(float %25, float %26) 36 %29 = bitcast i32 %28 to float 37 %30 = call i32 @llvm.SI.packf16(float %27, float 1.000000e+00) 38 %31 = bitcast i32 %30 to float 39 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31) 40 ret void 41 } 42 43 ; Function Attrs: readnone 44 declare float @fabs(float) #2 45 46 ; Function Attrs: nounwind readnone 47 declare i32 @llvm.SI.packf16(float, float) #1 48 49 ; Function Attrs: nounwind readnone 50 declare float @llvm.SI.fs.constant(i32, i32, i32) #1 51 52 ; Function Attrs: nounwind readnone 53 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 54 55 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 56 57 attributes #0 = { "ShaderType"="0" } 58 attributes #1 = { nounwind readnone } 59 attributes #2 = { readnone } 60
