1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s 2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4 ;CHECK-LABEL: {{^}}sample: 5 ;CHECK: s_wqm 6 ;CHECK: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 7 define void @sample() #0 { 8 main_body: 9 %r = call <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 10 %r0 = extractelement <4 x float> %r, i32 0 11 %r1 = extractelement <4 x float> %r, i32 1 12 %r2 = extractelement <4 x float> %r, i32 2 13 %r3 = extractelement <4 x float> %r, i32 3 14 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 15 ret void 16 } 17 18 ;CHECK-LABEL: {{^}}sample_cl: 19 ;CHECK: s_wqm 20 ;CHECK: image_sample_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 21 define void @sample_cl() #0 { 22 main_body: 23 %r = call <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 24 %r0 = extractelement <4 x float> %r, i32 0 25 %r1 = extractelement <4 x float> %r, i32 1 26 %r2 = extractelement <4 x float> %r, i32 2 27 %r3 = extractelement <4 x float> %r, i32 3 28 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 29 ret void 30 } 31 32 ;CHECK-LABEL: {{^}}sample_d: 33 ;CHECK-NOT: s_wqm 34 ;CHECK: image_sample_d_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 35 define void @sample_d() #0 { 36 main_body: 37 %r = call <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 38 %r0 = extractelement <4 x float> %r, i32 0 39 %r1 = extractelement <4 x float> %r, i32 1 40 %r2 = extractelement <4 x float> %r, i32 2 41 %r3 = extractelement <4 x float> %r, i32 3 42 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 43 ret void 44 } 45 46 ;CHECK-LABEL: {{^}}sample_d_cl: 47 ;CHECK-NOT: s_wqm 48 ;CHECK: image_sample_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 49 define void @sample_d_cl() #0 { 50 main_body: 51 %r = call <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 52 %r0 = extractelement <4 x float> %r, i32 0 53 %r1 = extractelement <4 x float> %r, i32 1 54 %r2 = extractelement <4 x float> %r, i32 2 55 %r3 = extractelement <4 x float> %r, i32 3 56 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 57 ret void 58 } 59 60 ;CHECK-LABEL: {{^}}sample_l: 61 ;CHECK-NOT: s_wqm 62 ;CHECK: image_sample_l_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 63 define void @sample_l() #0 { 64 main_body: 65 %r = call <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 66 %r0 = extractelement <4 x float> %r, i32 0 67 %r1 = extractelement <4 x float> %r, i32 1 68 %r2 = extractelement <4 x float> %r, i32 2 69 %r3 = extractelement <4 x float> %r, i32 3 70 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 71 ret void 72 } 73 74 ;CHECK-LABEL: {{^}}sample_b: 75 ;CHECK: s_wqm 76 ;CHECK: image_sample_b_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 77 define void @sample_b() #0 { 78 main_body: 79 %r = call <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 80 %r0 = extractelement <4 x float> %r, i32 0 81 %r1 = extractelement <4 x float> %r, i32 1 82 %r2 = extractelement <4 x float> %r, i32 2 83 %r3 = extractelement <4 x float> %r, i32 3 84 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 85 ret void 86 } 87 88 ;CHECK-LABEL: {{^}}sample_b_cl: 89 ;CHECK: s_wqm 90 ;CHECK: image_sample_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 91 define void @sample_b_cl() #0 { 92 main_body: 93 %r = call <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 94 %r0 = extractelement <4 x float> %r, i32 0 95 %r1 = extractelement <4 x float> %r, i32 1 96 %r2 = extractelement <4 x float> %r, i32 2 97 %r3 = extractelement <4 x float> %r, i32 3 98 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 99 ret void 100 } 101 102 ;CHECK-LABEL: {{^}}sample_lz: 103 ;CHECK-NOT: s_wqm 104 ;CHECK: image_sample_lz_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 105 define void @sample_lz() #0 { 106 main_body: 107 %r = call <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 108 %r0 = extractelement <4 x float> %r, i32 0 109 %r1 = extractelement <4 x float> %r, i32 1 110 %r2 = extractelement <4 x float> %r, i32 2 111 %r3 = extractelement <4 x float> %r, i32 3 112 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 113 ret void 114 } 115 116 ;CHECK-LABEL: {{^}}sample_cd: 117 ;CHECK-NOT: s_wqm 118 ;CHECK: image_sample_cd_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 119 define void @sample_cd() #0 { 120 main_body: 121 %r = call <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 122 %r0 = extractelement <4 x float> %r, i32 0 123 %r1 = extractelement <4 x float> %r, i32 1 124 %r2 = extractelement <4 x float> %r, i32 2 125 %r3 = extractelement <4 x float> %r, i32 3 126 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 127 ret void 128 } 129 130 ;CHECK-LABEL: {{^}}sample_cd_cl: 131 ;CHECK-NOT: s_wqm 132 ;CHECK: image_sample_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 133 define void @sample_cd_cl() #0 { 134 main_body: 135 %r = call <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 136 %r0 = extractelement <4 x float> %r, i32 0 137 %r1 = extractelement <4 x float> %r, i32 1 138 %r2 = extractelement <4 x float> %r, i32 2 139 %r3 = extractelement <4 x float> %r, i32 3 140 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 141 ret void 142 } 143 144 ;CHECK-LABEL: {{^}}sample_c: 145 ;CHECK: s_wqm 146 ;CHECK: image_sample_c_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 147 define void @sample_c() #0 { 148 main_body: 149 %r = call <4 x float> @llvm.SI.image.sample.c.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 150 %r0 = extractelement <4 x float> %r, i32 0 151 %r1 = extractelement <4 x float> %r, i32 1 152 %r2 = extractelement <4 x float> %r, i32 2 153 %r3 = extractelement <4 x float> %r, i32 3 154 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 155 ret void 156 } 157 158 ;CHECK-LABEL: {{^}}sample_c_cl: 159 ;CHECK: s_wqm 160 ;CHECK: image_sample_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 161 define void @sample_c_cl() #0 { 162 main_body: 163 %r = call <4 x float> @llvm.SI.image.sample.c.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 164 %r0 = extractelement <4 x float> %r, i32 0 165 %r1 = extractelement <4 x float> %r, i32 1 166 %r2 = extractelement <4 x float> %r, i32 2 167 %r3 = extractelement <4 x float> %r, i32 3 168 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 169 ret void 170 } 171 172 ;CHECK-LABEL: {{^}}sample_c_d: 173 ;CHECK-NOT: s_wqm 174 ;CHECK: image_sample_c_d_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 175 define void @sample_c_d() #0 { 176 main_body: 177 %r = call <4 x float> @llvm.SI.image.sample.c.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 178 %r0 = extractelement <4 x float> %r, i32 0 179 %r1 = extractelement <4 x float> %r, i32 1 180 %r2 = extractelement <4 x float> %r, i32 2 181 %r3 = extractelement <4 x float> %r, i32 3 182 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 183 ret void 184 } 185 186 ;CHECK-LABEL: {{^}}sample_c_d_cl: 187 ;CHECK-NOT: s_wqm 188 ;CHECK: image_sample_c_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 189 define void @sample_c_d_cl() #0 { 190 main_body: 191 %r = call <4 x float> @llvm.SI.image.sample.c.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 192 %r0 = extractelement <4 x float> %r, i32 0 193 %r1 = extractelement <4 x float> %r, i32 1 194 %r2 = extractelement <4 x float> %r, i32 2 195 %r3 = extractelement <4 x float> %r, i32 3 196 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 197 ret void 198 } 199 200 ;CHECK-LABEL: {{^}}sample_c_l: 201 ;CHECK-NOT: s_wqm 202 ;CHECK: image_sample_c_l_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 203 define void @sample_c_l() #0 { 204 main_body: 205 %r = call <4 x float> @llvm.SI.image.sample.c.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 206 %r0 = extractelement <4 x float> %r, i32 0 207 %r1 = extractelement <4 x float> %r, i32 1 208 %r2 = extractelement <4 x float> %r, i32 2 209 %r3 = extractelement <4 x float> %r, i32 3 210 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 211 ret void 212 } 213 214 ;CHECK-LABEL: {{^}}sample_c_b: 215 ;CHECK: s_wqm 216 ;CHECK: image_sample_c_b_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 217 define void @sample_c_b() #0 { 218 main_body: 219 %r = call <4 x float> @llvm.SI.image.sample.c.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 220 %r0 = extractelement <4 x float> %r, i32 0 221 %r1 = extractelement <4 x float> %r, i32 1 222 %r2 = extractelement <4 x float> %r, i32 2 223 %r3 = extractelement <4 x float> %r, i32 3 224 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 225 ret void 226 } 227 228 ;CHECK-LABEL: {{^}}sample_c_b_cl: 229 ;CHECK: s_wqm 230 ;CHECK: image_sample_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 231 define void @sample_c_b_cl() #0 { 232 main_body: 233 %r = call <4 x float> @llvm.SI.image.sample.c.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 234 %r0 = extractelement <4 x float> %r, i32 0 235 %r1 = extractelement <4 x float> %r, i32 1 236 %r2 = extractelement <4 x float> %r, i32 2 237 %r3 = extractelement <4 x float> %r, i32 3 238 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 239 ret void 240 } 241 242 ;CHECK-LABEL: {{^}}sample_c_lz: 243 ;CHECK-NOT: s_wqm 244 ;CHECK: image_sample_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 245 define void @sample_c_lz() #0 { 246 main_body: 247 %r = call <4 x float> @llvm.SI.image.sample.c.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 248 %r0 = extractelement <4 x float> %r, i32 0 249 %r1 = extractelement <4 x float> %r, i32 1 250 %r2 = extractelement <4 x float> %r, i32 2 251 %r3 = extractelement <4 x float> %r, i32 3 252 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 253 ret void 254 } 255 256 ;CHECK-LABEL: {{^}}sample_c_cd: 257 ;CHECK-NOT: s_wqm 258 ;CHECK: image_sample_c_cd_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 259 define void @sample_c_cd() #0 { 260 main_body: 261 %r = call <4 x float> @llvm.SI.image.sample.c.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 262 %r0 = extractelement <4 x float> %r, i32 0 263 %r1 = extractelement <4 x float> %r, i32 1 264 %r2 = extractelement <4 x float> %r, i32 2 265 %r3 = extractelement <4 x float> %r, i32 3 266 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 267 ret void 268 } 269 270 ;CHECK-LABEL: {{^}}sample_c_cd_cl: 271 ;CHECK-NOT: s_wqm 272 ;CHECK: image_sample_c_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} 273 define void @sample_c_cd_cl() #0 { 274 main_body: 275 %r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) 276 %r0 = extractelement <4 x float> %r, i32 0 277 %r1 = extractelement <4 x float> %r, i32 1 278 %r2 = extractelement <4 x float> %r, i32 2 279 %r3 = extractelement <4 x float> %r, i32 3 280 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) 281 ret void 282 } 283 284 285 declare <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 286 declare <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 287 declare <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 288 declare <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 289 declare <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 290 declare <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 291 declare <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 292 declare <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 293 declare <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 294 declare <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 295 296 declare <4 x float> @llvm.SI.image.sample.c.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 297 declare <4 x float> @llvm.SI.image.sample.c.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 298 declare <4 x float> @llvm.SI.image.sample.c.d.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 299 declare <4 x float> @llvm.SI.image.sample.c.d.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 300 declare <4 x float> @llvm.SI.image.sample.c.l.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 301 declare <4 x float> @llvm.SI.image.sample.c.b.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 302 declare <4 x float> @llvm.SI.image.sample.c.b.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 303 declare <4 x float> @llvm.SI.image.sample.c.lz.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 304 declare <4 x float> @llvm.SI.image.sample.c.cd.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 305 declare <4 x float> @llvm.SI.image.sample.c.cd.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 306 307 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) 308 309 attributes #0 = { "ShaderType"="0" } 310 attributes #1 = { nounwind readnone } 311
