1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC 2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC 3 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC 4 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC 5 6 declare i32 @llvm.AMDGPU.imul24(i32, i32) nounwind readnone 7 8 ; FUNC-LABEL: {{^}}i32_mad24: 9 ; Signed 24-bit multiply is not supported on pre-Cayman GPUs. 10 ; EG: MULLO_INT 11 ; Make sure we aren't masking the inputs. 12 ; CM-NOT: AND 13 ; CM: MULADD_INT24 14 ; SI-NOT: and 15 ; SI: v_mad_i32_i24 16 define void @i32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 17 entry: 18 %0 = shl i32 %a, 8 19 %a_24 = ashr i32 %0, 8 20 %1 = shl i32 %b, 8 21 %b_24 = ashr i32 %1, 8 22 %2 = mul i32 %a_24, %b_24 23 %3 = add i32 %2, %c 24 store i32 %3, i32 addrspace(1)* %out 25 ret void 26 } 27 28 ; FUNC-LABEL: @test_imul24 29 ; SI: v_mad_i32_i24 30 define void @test_imul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { 31 %mul = call i32 @llvm.AMDGPU.imul24(i32 %src0, i32 %src1) nounwind readnone 32 %add = add i32 %mul, %src2 33 store i32 %add, i32 addrspace(1)* %out, align 4 34 ret void 35 } 36
