1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s 3 4 ; Make sure there isn't an extra space between the instruction name and first operands. 5 6 ; GCN-LABEL: {{^}}add_f32: 7 ; SI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb 8 ; SI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc 9 ; VI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c 10 ; VI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 11 ; GCN: v_mov_b32_e32 [[VREGB:v[0-9]+]], [[SREGB]] 12 ; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]] 13 ; GCN: buffer_store_dword [[RESULT]], 14 define void @add_f32(float addrspace(1)* %out, float %a, float %b) { 15 %result = fadd float %a, %b 16 store float %result, float addrspace(1)* %out 17 ret void 18 } 19
