1 ; RUN: llc -march=amdgcn -verify-machineinstrs -verify-coalescing < %s 2 3 ; The original and requires materializing a 64-bit immediate for 4 ; s_and_b64. This is split into 2 x v_and_i32, part of the immediate 5 ; is folded through the reg_sequence into the v_and_i32 operand, and 6 ; only half of the result is ever used. 7 ; 8 ; During live interval construction, the first sub register def is 9 ; incorrectly marked as dead. 10 11 declare i32 @llvm.r600.read.tidig.x() #1 12 13 define void @dead_def_subregister(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) #0 { 14 %tid = call i32 @llvm.r600.read.tidig.x() #1 15 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 16 %val = load i64, i64 addrspace(1)* %in.gep 17 18 %lshr = shl i64 %val, 24 19 %and1 = and i64 %lshr, 2190433320969 ; (255 << 33) | 9 20 %vec = bitcast i64 %and1 to <2 x i32> 21 %elt1 = extractelement <2 x i32> %vec, i32 1 22 23 store i32 %elt1, i32 addrspace(1)* %out 24 ret void 25 } 26 27 attributes #0 = { nounwind } 28 attributes #1 = { nounwind readnone } 29
