1 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG %s 2 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s 3 4 ; The earliest R600 GPUs have a slightly different encoding than the rest of 5 ; the VLIW4/5 GPUs. 6 7 ; EG: {{^}}test: 8 ; EG: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}] 9 10 ; R600: {{^}}test: 11 ; R600: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}] 12 13 define void @test(<4 x float> inreg %reg0) #0 { 14 entry: 15 %r0 = extractelement <4 x float> %reg0, i32 0 16 %r1 = extractelement <4 x float> %reg0, i32 1 17 %r2 = fmul float %r0, %r1 18 %vec = insertelement <4 x float> undef, float %r2, i32 0 19 call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) 20 ret void 21 } 22 23 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) 24 25 attributes #0 = { "ShaderType"="0" } 26
