1 ; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -o - %s \ 2 ; RUN: | FileCheck %s -check-prefix CHECK-SMALL-CODE 3 ; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -code-model=large -o - %s \ 4 ; RUN: | FileCheck %s -check-prefix CHECK-LARGE-CODE 5 ; RUN: llc -mtriple=thumbv7-windows-msvc -mcpu=cortex-a9 -o - %s \ 6 ; RUN: | FileCheck %s -check-prefix CHECK-MSVC 7 8 define arm_aapcs_vfpcc i8 @function(i32 %sz, i32 %idx) { 9 entry: 10 %vla = alloca i8, i32 %sz, align 1 11 %arrayidx = getelementptr inbounds i8, i8* %vla, i32 %idx 12 %0 = load volatile i8, i8* %arrayidx, align 1 13 ret i8 %0 14 } 15 16 ; CHECK-SMALL-CODE: adds [[R4:r[0-9]+]], #7 17 ; CHECK-SMALL-CODE: bic [[R4]], [[R4]], #7 18 ; CHECK-SMALL-CODE: lsrs r4, [[R4]], #2 19 ; CHECK-SMALL-CODE: bl __chkstk 20 ; CHECK-SMALL-CODE: sub.w sp, sp, r4 21 22 ; CHECK-LARGE-CODE: adds [[R4:r[0-9]+]], #7 23 ; CHECK-LARGE-CODE: bic [[R4]], [[R4]], #7 24 ; CHECK-LARGE-CODE: lsrs r4, [[R4]], #2 25 ; CHECK-LARGE-CODE: movw [[IP:r[0-9]+]], :lower16:__chkstk 26 ; CHECK-LARGE-CODE: movt [[IP]], :upper16:__chkstk 27 ; CHECK-LARGE-CODE: blx [[IP]] 28 ; CHECK-LARGE-CODE: sub.w sp, sp, r4 29 30 ; CHECK-MSVC-NOT: __chkstk 31 32
