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      1 ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
      2 ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
      3 
      4 define i32 @shl() nounwind ssp {
      5 entry:
      6 ; ARM: shl
      7 ; ARM: lsl r0, r0, #2
      8   %shl = shl i32 -1, 2
      9   ret i32 %shl
     10 }
     11 
     12 define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp {
     13 entry:
     14 ; ARM: shl_reg
     15 ; ARM: lsl r0, r0, r1
     16   %shl = shl i32 %src1, %src2
     17   ret i32 %shl
     18 }
     19 
     20 define i32 @lshr() nounwind ssp {
     21 entry:
     22 ; ARM: lshr
     23 ; ARM: lsr r0, r0, #2
     24   %lshr = lshr i32 -1, 2
     25   ret i32 %lshr
     26 }
     27 
     28 define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp {
     29 entry:
     30 ; ARM: lshr_reg
     31 ; ARM: lsr r0, r0, r1
     32   %lshr = lshr i32 %src1, %src2
     33   ret i32 %lshr
     34 }
     35 
     36 define i32 @ashr() nounwind ssp {
     37 entry:
     38 ; ARM: ashr
     39 ; ARM: asr r0, r0, #2
     40   %ashr = ashr i32 -1, 2
     41   ret i32 %ashr
     42 }
     43 
     44 define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp {
     45 entry:
     46 ; ARM: ashr_reg
     47 ; ARM: asr r0, r0, r1
     48   %ashr = ashr i32 %src1, %src2
     49   ret i32 %ashr
     50 }
     51 
     52