1 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ 2 ; RUN: < %s | FileCheck %s 3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ 4 ; RUN: < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ 6 ; RUN: < %s | FileCheck %s -check-prefix=mips32r2 7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ 8 ; RUN: < %s | FileCheck %s -check-prefix=mips32 9 10 @b2 = global i8 0, align 1 11 @b1 = global i8 1, align 1 12 @uc1 = global i8 0, align 1 13 @uc2 = global i8 -1, align 1 14 @sc1 = global i8 -128, align 1 15 @sc2 = global i8 127, align 1 16 @ss1 = global i16 -32768, align 2 17 @ss2 = global i16 32767, align 2 18 @us1 = global i16 0, align 2 19 @us2 = global i16 -1, align 2 20 @ssi = global i16 0, align 2 21 @ssj = global i16 0, align 2 22 @i = global i32 0, align 4 23 @j = global i32 0, align 4 24 @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 25 @.str1 = private unnamed_addr constant [7 x i8] c"%i %i\0A\00", align 1 26 27 ; Function Attrs: nounwind 28 define void @_Z3b_iv() { 29 entry: 30 ; CHECK-LABEL: .ent _Z3b_iv 31 %0 = load i8, i8* @b1, align 1 32 %tobool = trunc i8 %0 to i1 33 %frombool = zext i1 %tobool to i8 34 store i8 %frombool, i8* @b2, align 1 35 %1 = load i8, i8* @b2, align 1 36 %tobool1 = trunc i8 %1 to i1 37 %conv = zext i1 %tobool1 to i32 38 store i32 %conv, i32* @i, align 4 39 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 40 ; CHECK: andi $[[REG2:[0-9]+]], $[[REG1]], 1 41 ; CHECK: sb $[[REG2]], 0(${{[0-9]+}}) 42 43 44 45 ret void 46 ; CHECK: .end _Z3b_iv 47 } 48 49 ; Function Attrs: nounwind 50 define void @_Z4uc_iv() { 51 entry: 52 ; CHECK-LABEL: .ent _Z4uc_iv 53 54 %0 = load i8, i8* @uc1, align 1 55 %conv = zext i8 %0 to i32 56 store i32 %conv, i32* @i, align 4 57 %1 = load i8, i8* @uc2, align 1 58 %conv1 = zext i8 %1 to i32 59 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 60 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255 61 62 store i32 %conv1, i32* @j, align 4 63 ret void 64 ; CHECK: .end _Z4uc_iv 65 66 } 67 68 ; Function Attrs: nounwind 69 define void @_Z4sc_iv() { 70 entry: 71 ; mips32r2-LABEL: .ent _Z4sc_iv 72 ; mips32-LABEL: .ent _Z4sc_iv 73 74 %0 = load i8, i8* @sc1, align 1 75 %conv = sext i8 %0 to i32 76 store i32 %conv, i32* @i, align 4 77 %1 = load i8, i8* @sc2, align 1 78 %conv1 = sext i8 %1 to i32 79 store i32 %conv1, i32* @j, align 4 80 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 81 ; mips32r2: seb ${{[0-9]+}}, $[[REG1]] 82 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 83 ; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24 84 ; mips32: sra ${{[0-9]+}}, $[[REG2]], 24 85 86 ret void 87 ; CHECK: .end _Z4sc_iv 88 } 89 90 ; Function Attrs: nounwind 91 define void @_Z4us_iv() { 92 entry: 93 ; CHECK-LABEL: .ent _Z4us_iv 94 %0 = load i16, i16* @us1, align 2 95 %conv = zext i16 %0 to i32 96 store i32 %conv, i32* @i, align 4 97 %1 = load i16, i16* @us2, align 2 98 %conv1 = zext i16 %1 to i32 99 store i32 %conv1, i32* @j, align 4 100 ret void 101 ; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 102 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 65535 103 ; CHECK: .end _Z4us_iv 104 } 105 106 ; Function Attrs: nounwind 107 define void @_Z4ss_iv() { 108 entry: 109 ; mips32r2-LABEL: .ent _Z4ss_iv 110 ; mips32=LABEL: .ent _Z4ss_iv 111 112 %0 = load i16, i16* @ss1, align 2 113 %conv = sext i16 %0 to i32 114 store i32 %conv, i32* @i, align 4 115 %1 = load i16, i16* @ss2, align 2 116 %conv1 = sext i16 %1 to i32 117 store i32 %conv1, i32* @j, align 4 118 ; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 119 ; mips32r2: seh ${{[0-9]+}}, $[[REG1]] 120 ; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 121 ; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16 122 ; mips32: sra ${{[0-9]+}}, $[[REG2]], 16 123 124 ret void 125 ; CHECK: .end _Z4ss_iv 126 } 127 128 ; Function Attrs: nounwind 129 define void @_Z4b_ssv() { 130 entry: 131 ; CHECK-LABEL: .ent _Z4b_ssv 132 %0 = load i8, i8* @b2, align 1 133 %tobool = trunc i8 %0 to i1 134 %conv = zext i1 %tobool to i16 135 store i16 %conv, i16* @ssi, align 2 136 ret void 137 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 138 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 139 ; CHECK: .end _Z4b_ssv 140 } 141 142 ; Function Attrs: nounwind 143 define void @_Z5uc_ssv() { 144 entry: 145 ; CHECK-LABEL: .ent _Z5uc_ssv 146 %0 = load i8, i8* @uc1, align 1 147 %conv = zext i8 %0 to i16 148 store i16 %conv, i16* @ssi, align 2 149 %1 = load i8, i8* @uc2, align 1 150 %conv1 = zext i8 %1 to i16 151 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 152 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255 153 154 store i16 %conv1, i16* @ssj, align 2 155 ret void 156 ; CHECK: .end _Z5uc_ssv 157 } 158 159 ; Function Attrs: nounwind 160 define void @_Z5sc_ssv() { 161 entry: 162 ; mips32r2-LABEL: .ent _Z5sc_ssv 163 ; mips32-LABEL: .ent _Z5sc_ssv 164 %0 = load i8, i8* @sc1, align 1 165 %conv = sext i8 %0 to i16 166 store i16 %conv, i16* @ssi, align 2 167 %1 = load i8, i8* @sc2, align 1 168 %conv1 = sext i8 %1 to i16 169 store i16 %conv1, i16* @ssj, align 2 170 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 171 ; mips32r2: seb ${{[0-9]+}}, $[[REG1]] 172 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 173 ; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24 174 ; mips32: sra ${{[0-9]+}}, $[[REG2]], 24 175 176 ret void 177 ; CHECK: .end _Z5sc_ssv 178 } 179 180
