1 ; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s 2 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s 3 ; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R6 -check-prefix=MIPS32-GT-R1 %s 4 ; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s 5 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s 6 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s 7 ; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s 8 9 ; Prefixes: 10 ; ALL - All 11 ; MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's) 12 ; MIPS64-GT-R1 - MIPS64r1 and above 13 14 define i32 @ctlz_i32(i32 signext %X) nounwind readnone { 15 entry: 16 ; ALL-LABEL: ctlz_i32: 17 18 ; MIPS4-NOT: clz 19 20 ; MIPS32-GT-R1: clz $2, $4 21 22 ; MIPS64-GT-R1: clz $2, $4 23 24 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) 25 ret i32 %tmp1 26 } 27 28 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone 29 30 define i32 @ctlo_i32(i32 signext %X) nounwind readnone { 31 entry: 32 ; ALL-LABEL: ctlo_i32: 33 34 ; MIPS4-NOT: clo 35 36 ; MIPS32-GT-R1: clo $2, $4 37 38 ; MIPS64-GT-R1: clo $2, $4 39 40 %neg = xor i32 %X, -1 41 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) 42 ret i32 %tmp1 43 } 44 45 define i64 @ctlz_i64(i64 %X) nounwind readnone { 46 entry: 47 ; ALL-LABEL: ctlz_i64: 48 49 ; MIPS4-NOT: dclz 50 51 ; MIPS32-GT-R1-DAG: clz $[[R0:[0-9]+]], $4 52 ; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5 53 ; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32 54 ; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $5 55 ; MIPS32-R6-DAG: seleqz $[[R5:[0-9]+]], $[[R2]], $5 56 ; MIPS32-R6-DAG: selnez $[[R6:[0-9]+]], $[[R1]], $5 57 ; MIPS32-R6-DAG: or $2, $[[R6]], $[[R5]] 58 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 59 60 ; MIPS64-GT-R1: dclz $2, $4 61 62 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) 63 ret i64 %tmp1 64 } 65 66 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone 67 68 define i64 @ctlo_i64(i64 %X) nounwind readnone { 69 entry: 70 ; ALL-LABEL: ctlo_i64: 71 72 ; MIPS4-NOT: dclo 73 74 ; MIPS32-GT-R1-DAG: clo $[[R0:[0-9]+]], $4 75 ; MIPS32-GT-R1-DAG: clo $[[R1:[0-9]+]], $5 76 ; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32 77 ; MIPS32-GT-R1-DAG: addiu $[[R3:[0-9]+]], $zero, -1 78 ; MIPS32-GT-R1-DAG: xor $[[R4:[0-9]+]], $5, $[[R3]] 79 ; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $[[R4]] 80 ; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R1]], $[[R4]] 81 ; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R2]], $[[R4]] 82 ; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]] 83 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 84 85 ; MIPS64-GT-R1: dclo $2, $4 86 87 %neg = xor i64 %X, -1 88 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) 89 ret i64 %tmp1 90 } 91
