1 ; Test the MSA intrinsics that are encoded with the I5 instruction format. 2 ; There are lots of these so this covers those beginning with 'a' 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7 @llvm_mips_addvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8 @llvm_mips_addvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 9 10 define void @llvm_mips_addvi_b_test() nounwind { 11 entry: 12 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_addvi_b_ARG1 13 %1 = tail call <16 x i8> @llvm.mips.addvi.b(<16 x i8> %0, i32 14) 14 store <16 x i8> %1, <16 x i8>* @llvm_mips_addvi_b_RES 15 ret void 16 } 17 18 declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32) nounwind 19 20 ; CHECK: llvm_mips_addvi_b_test: 21 ; CHECK: ld.b 22 ; CHECK: addvi.b 23 ; CHECK: st.b 24 ; CHECK: .size llvm_mips_addvi_b_test 25 ; 26 @llvm_mips_addvi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 27 @llvm_mips_addvi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 28 29 define void @llvm_mips_addvi_h_test() nounwind { 30 entry: 31 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_addvi_h_ARG1 32 %1 = tail call <8 x i16> @llvm.mips.addvi.h(<8 x i16> %0, i32 14) 33 store <8 x i16> %1, <8 x i16>* @llvm_mips_addvi_h_RES 34 ret void 35 } 36 37 declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32) nounwind 38 39 ; CHECK: llvm_mips_addvi_h_test: 40 ; CHECK: ld.h 41 ; CHECK: addvi.h 42 ; CHECK: st.h 43 ; CHECK: .size llvm_mips_addvi_h_test 44 ; 45 @llvm_mips_addvi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 46 @llvm_mips_addvi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 47 48 define void @llvm_mips_addvi_w_test() nounwind { 49 entry: 50 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_addvi_w_ARG1 51 %1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 14) 52 store <4 x i32> %1, <4 x i32>* @llvm_mips_addvi_w_RES 53 ret void 54 } 55 56 declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32) nounwind 57 58 ; CHECK: llvm_mips_addvi_w_test: 59 ; CHECK: ld.w 60 ; CHECK: addvi.w 61 ; CHECK: st.w 62 ; CHECK: .size llvm_mips_addvi_w_test 63 ; 64 @llvm_mips_addvi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 65 @llvm_mips_addvi_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 66 67 define void @llvm_mips_addvi_d_test() nounwind { 68 entry: 69 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_addvi_d_ARG1 70 %1 = tail call <2 x i64> @llvm.mips.addvi.d(<2 x i64> %0, i32 14) 71 store <2 x i64> %1, <2 x i64>* @llvm_mips_addvi_d_RES 72 ret void 73 } 74 75 declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32) nounwind 76 77 ; CHECK: llvm_mips_addvi_d_test: 78 ; CHECK: ld.d 79 ; CHECK: addvi.d 80 ; CHECK: st.d 81 ; CHECK: .size llvm_mips_addvi_d_test 82 ; 83
