1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s 2 3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" 4 target triple = "nvptx64-nvidia-cuda" 5 6 ; Function Attrs: nounwind 7 ; CHECK: .func kernelgen_memcpy 8 define ptx_device void @kernelgen_memcpy(i8* nocapture %dst) #0 { 9 entry: 10 br i1 undef, label %for.end, label %vector.body 11 12 vector.body: ; preds = %vector.body, %entry 13 %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ] 14 %scevgep9 = getelementptr i8, i8* %dst, i64 %index 15 %scevgep910 = bitcast i8* %scevgep9 to <4 x i8>* 16 store <4 x i8> undef, <4 x i8>* %scevgep910, align 1 17 %index.next = add i64 %index, 4 18 %0 = icmp eq i64 undef, %index.next 19 br i1 %0, label %middle.block, label %vector.body 20 21 middle.block: ; preds = %vector.body 22 br i1 undef, label %for.end, label %for.body.preheader1 23 24 for.body.preheader1: ; preds = %middle.block 25 %scevgep2 = getelementptr i8, i8* %dst, i64 0 26 br label %for.body 27 28 for.body: ; preds = %for.body, %for.body.preheader1 29 %lsr.iv3 = phi i8* [ %scevgep2, %for.body.preheader1 ], [ %scevgep4, %for.body ] 30 store i8 undef, i8* %lsr.iv3, align 1 31 %scevgep4 = getelementptr i8, i8* %lsr.iv3, i64 1 32 br label %for.body 33 34 for.end: ; preds = %middle.block, %entry 35 ret void 36 } 37 38 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } 39
