1 ; RUN: llc -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s 2 target datalayout = "E-m:e-i64:64-n32:64" 3 target triple = "powerpc64-unknown-linux-gnu" 4 5 define zeroext i32 @test1() { 6 entry: 7 %0 = tail call i32 @llvm.ppc.tbegin(i32 0) 8 ret i32 %0 9 10 ; CHECK-LABEL: @test1 11 ; CHECK: tbegin. 0 12 ; CHECK: mfocrf [[REGISTER1:[0-9]+]], 128 13 ; CHECK: rlwinm [[REGISTER2:[0-9]+]], [[REGISTER1]], 3, 31, 31 14 ; CHECK: xori {{[0-9]+}}, [[REGISTER2]], 1 15 } 16 17 declare i32 @llvm.ppc.tbegin(i32) #1 18 19 20 define zeroext i32 @test2() { 21 entry: 22 %0 = tail call i32 @llvm.ppc.tend(i32 0) 23 ret i32 %0 24 ; CHECK-LABEL: @test2 25 ; CHECK: tend. 0 26 ; CHECK: mfocrf {{[0-9]+}}, 128 27 } 28 29 declare i32 @llvm.ppc.tend(i32) 30 31 32 define void @test3() { 33 entry: 34 %0 = tail call i32 @llvm.ppc.tabort(i32 0) 35 %1 = tail call i32 @llvm.ppc.tabortdc(i32 0, i32 1, i32 2) 36 %2 = tail call i32 @llvm.ppc.tabortdci(i32 0, i32 1, i32 2) 37 %3 = tail call i32 @llvm.ppc.tabortwc(i32 0, i32 1, i32 2) 38 %4 = tail call i32 @llvm.ppc.tabortwci(i32 0, i32 1, i32 2) 39 ret void 40 ; CHECK-LABEL: @test3 41 ; CHECK: tabort. {{[0-9]+}} 42 ; CHECK: tabortdc. 0, {{[0-9]+}}, {{[0-9]+}} 43 ; CHECK: tabortdci. 0, {{[0-9]+}}, 2 44 ; CHECK: tabortwc. 0, {{[0-9]+}}, {{[0-9]+}} 45 ; CHECK: tabortwci. 0, {{[0-9]+}}, 2 46 } 47 48 declare i32 @llvm.ppc.tabort(i32) 49 declare i32 @llvm.ppc.tabortdc(i32, i32, i32) 50 declare i32 @llvm.ppc.tabortdci(i32, i32, i32) 51 declare i32 @llvm.ppc.tabortwc(i32, i32, i32) 52 declare i32 @llvm.ppc.tabortwci(i32, i32, i32) 53 54 55 define void @test4() { 56 entry: 57 %0 = tail call i32 @llvm.ppc.tendall() 58 %1 = tail call i32 @llvm.ppc.tresume() 59 %2 = tail call i32 @llvm.ppc.tsuspend() 60 ret void 61 ; CHECK-LABEL: @test4 62 ; CHECK: tend. 1 63 ; CHECK: tsr. 1 64 ; CHECK: tsr. 0 65 } 66 67 declare i32 @llvm.ppc.tendall() 68 declare i32 @llvm.ppc.tresume() 69 declare i32 @llvm.ppc.tsuspend() 70 71 72 define void @test5(i64 %v) { 73 entry: 74 tail call void @llvm.ppc.set.texasr(i64 %v) 75 tail call void @llvm.ppc.set.texasru(i64 %v) 76 tail call void @llvm.ppc.set.tfhar(i64 %v) 77 tail call void @llvm.ppc.set.tfiar(i64 %v) 78 ret void 79 ; CHECK-LABEL: @test5 80 ; CHECK: mtspr 130, [[REG1:[0-9]+]] 81 ; CHECK: mtspr 131, [[REG2:[0-9]+]] 82 ; CHECK: mtspr 128, [[REG3:[0-9]+]] 83 ; CHECK: mtspr 129, [[REG4:[0-9]+]] 84 } 85 86 define i64 @test6() { 87 entry: 88 %0 = tail call i64 @llvm.ppc.get.texasr() 89 ret i64 %0 90 ; CHECK-LABEL: @test6 91 ; CHECK: mfspr [[REG1:[0-9]+]], 130 92 } 93 94 define i64 @test7() { 95 entry: 96 %0 = tail call i64 @llvm.ppc.get.texasru() 97 ret i64 %0 98 ; CHECK-LABEL: @test7 99 ; CHECK: mfspr [[REG1:[0-9]+]], 131 100 } 101 102 define i64 @test8() { 103 entry: 104 %0 = tail call i64 @llvm.ppc.get.tfhar() 105 ret i64 %0 106 ; CHECK-LABEL: @test8 107 ; CHECK: mfspr [[REG1:[0-9]+]], 128 108 } 109 110 define i64 @test9() { 111 entry: 112 %0 = tail call i64 @llvm.ppc.get.tfiar() 113 ret i64 %0 114 ; CHECK-LABEL: @test9 115 ; CHECK: mfspr [[REG1:[0-9]+]], 129 116 } 117 118 declare void @llvm.ppc.set.texasr(i64) 119 declare void @llvm.ppc.set.texasru(i64) 120 declare void @llvm.ppc.set.tfhar(i64) 121 declare void @llvm.ppc.set.tfiar(i64) 122 declare i64 @llvm.ppc.get.texasr() 123 declare i64 @llvm.ppc.get.texasru() 124 declare i64 @llvm.ppc.get.tfhar() 125 declare i64 @llvm.ppc.get.tfiar() 126
