1 ; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s 2 ; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s 3 4 define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { 5 %tmp = load <4 x i32>, <4 x i32>* %P1 ; <<4 x i32>> [#uses=1] 6 %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1] 7 store <4 x i32> %tmp4, <4 x i32>* %P1 8 %tmp7 = load <4 x i32>, <4 x i32>* %P2 ; <<4 x i32>> [#uses=1] 9 %tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1] 10 store <4 x i32> %tmp9, <4 x i32>* %P2 11 %tmp.upgrd.1 = load <4 x float>, <4 x float>* %P3 ; <<4 x float>> [#uses=1] 12 %tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32> ; <<4 x i32>> [#uses=1] 13 %tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1] 14 %tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1] 15 store <4 x float> %tmp13, <4 x float>* %P3 16 ret void 17 18 ; CHECK-LABEL: test1: 19 ; CHECK-NOT: CPI 20 } 21 22 define <4 x i32> @test_30() nounwind { 23 ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 > 24 25 ; CHECK-LABEL: test_30: 26 ; CHECK: vspltisw 27 ; CHECK-NEXT: vadduwm 28 ; CHECK-NEXT: blr 29 } 30 31 define <4 x i32> @test_29() nounwind { 32 ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 > 33 34 ; CHECK-LABEL: test_29: 35 ; CHECK: vspltisw 36 ; CHECK-NEXT: vspltisw 37 ; CHECK-NEXT: vsubuwm 38 ; CHECK-NEXT: blr 39 } 40 41 define <8 x i16> @test_n30() nounwind { 42 ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 > 43 44 ; CHECK-LABEL: test_n30: 45 ; CHECK: vspltish 46 ; CHECK-NEXT: vadduhm 47 ; CHECK-NEXT: blr 48 } 49 50 define <16 x i8> @test_n104() nounwind { 51 ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 > 52 53 ; CHECK-LABEL: test_n104: 54 ; CHECK: vspltisb 55 ; CHECK-NEXT: vslb 56 ; CHECK-NEXT: blr 57 } 58 59 define <4 x i32> @test_vsldoi() nounwind { 60 ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 > 61 62 ; CHECK-LABEL: test_vsldoi: 63 ; CHECK: vspltisw 64 ; CHECK-NEXT: vsldoi 65 ; CHECK-NEXT: blr 66 } 67 68 define <8 x i16> @test_vsldoi_65023() nounwind { 69 ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 > 70 71 ; CHECK-LABEL: test_vsldoi_65023: 72 ; CHECK: vspltish 73 ; CHECK-NEXT: vsldoi 74 ; CHECK-NEXT: blr 75 } 76 77 define <4 x i32> @test_rol() nounwind { 78 ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > 79 80 ; CHECK-LABEL: test_rol: 81 ; CHECK: vspltisw 82 ; CHECK-NEXT: vrlw 83 ; CHECK-NEXT: blr 84 } 85
