1 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s 2 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s 3 define void @test1sp(float %a, float %b, float %c, float %e, float* nocapture %d) #0 { 4 entry: 5 %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a) 6 store float %0, float* %d, align 4 7 %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a) 8 %arrayidx1 = getelementptr inbounds float, float* %d, i64 1 9 store float %1, float* %arrayidx1, align 4 10 ret void 11 12 ; CHECK-LABEL: @test1sp 13 ; CHECK-DAG: li [[C1:[0-9]+]], 4 14 ; CHECK-DAG: xsmaddmsp 3, 2, 1 15 ; CHECK-DAG: xsmaddasp 1, 2, 4 16 ; CHECK-DAG: stxsspx 3, 0, 7 17 ; CHECK-DAG: stxsspx 1, 7, [[C1]] 18 ; CHECK: blr 19 20 ; CHECK-FISL-LABEL: @test1sp 21 ; CHECK-FISL-DAG: fmr 0, 1 22 ; CHECK-FISL-DAG: xsmaddasp 0, 2, 3 23 ; CHECK-FISL-DAG: stxsspx 0, 0, 7 24 ; CHECK-FISL-DAG: xsmaddasp 1, 2, 4 25 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 4 26 ; CHECK-FISL-DAG: stxsspx 1, 7, [[C1]] 27 ; CHECK-FISL: blr 28 } 29 30 define void @test2sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 { 31 entry: 32 %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a) 33 store float %0, float* %d, align 4 34 %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a) 35 %arrayidx1 = getelementptr inbounds float, float* %d, i64 1 36 store float %1, float* %arrayidx1, align 4 37 %2 = tail call float @llvm.fma.f32(float %b, float %f, float %a) 38 %arrayidx2 = getelementptr inbounds float, float* %d, i64 2 39 store float %2, float* %arrayidx2, align 4 40 ret void 41 42 ; CHECK-LABEL: @test2sp 43 ; CHECK-DAG: li [[C1:[0-9]+]], 4 44 ; CHECK-DAG: li [[C2:[0-9]+]], 8 45 ; FIXME: We now miss this because of copy ordering at the MI level. 46 ; CHECX-DAG: xsmaddmsp 3, 2, 1 47 ; CHECX-DAG: xsmaddmsp 4, 2, 1 48 ; CHECX-DAG: xsmaddasp 1, 2, 5 49 ; CHECX-DAG: stxsspx 3, 0, 8 50 ; CHECX-DAG: stxsspx 4, 8, [[C1]] 51 ; CHECX-DAG: stxsspx 1, 8, [[C2]] 52 ; CHECK: blr 53 54 ; CHECK-FISL-LABEL: @test2sp 55 ; CHECK-FISL-DAG: fmr 0, 1 56 ; CHECK-FISL-DAG: xsmaddasp 0, 2, 3 57 ; CHECK-FISL-DAG: stxsspx 0, 0, 8 58 ; CHECK-FISL-DAG: fmr 0, 1 59 ; CHECK-FISL-DAG: xsmaddasp 0, 2, 4 60 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 4 61 ; CHECK-FISL-DAG: stxsspx 0, 8, [[C1]] 62 ; CHECK-FISL-DAG: xsmaddasp 1, 2, 5 63 ; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8 64 ; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]] 65 ; CHECK-FISL: blr 66 } 67 68 define void @test3sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 { 69 entry: 70 %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a) 71 store float %0, float* %d, align 4 72 %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a) 73 %2 = tail call float @llvm.fma.f32(float %b, float %c, float %1) 74 %arrayidx1 = getelementptr inbounds float, float* %d, i64 3 75 store float %2, float* %arrayidx1, align 4 76 %3 = tail call float @llvm.fma.f32(float %b, float %f, float %a) 77 %arrayidx2 = getelementptr inbounds float, float* %d, i64 2 78 store float %3, float* %arrayidx2, align 4 79 %arrayidx3 = getelementptr inbounds float, float* %d, i64 1 80 store float %1, float* %arrayidx3, align 4 81 ret void 82 83 ; CHECK-LABEL: @test3sp 84 ; CHECK-DAG: fmr [[F1:[0-9]+]], 1 85 ; CHECK-DAG: li [[C1:[0-9]+]], 12 86 ; CHECK-DAG: li [[C2:[0-9]+]], 8 87 ; CHECK-DAG: li [[C3:[0-9]+]], 4 88 ; CHECK-DAG: xsmaddmsp 4, 2, 1 89 ; CHECK-DAG: xsmaddasp 1, 2, 5 90 91 ; Note: We could convert this next FMA to M-type as well, but it would require 92 ; re-ordering the instructions. 93 ; CHECK-DAG: xsmaddasp [[F1]], 2, 3 94 95 ; CHECK-DAG: xsmaddmsp 3, 2, 4 96 ; CHECK-DAG: stxsspx [[F1]], 0, 8 97 ; CHECK-DAG: stxsspx 3, 8, [[C1]] 98 ; CHECK-DAG: stxsspx 1, 8, [[C2]] 99 ; CHECK-DAG: stxsspx 4, 8, [[C3]] 100 ; CHECK: blr 101 102 ; CHECK-FISL-LABEL: @test3sp 103 ; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1 104 ; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 4 105 ; CHECK-FISL-DAG: fmr 4, [[F1]] 106 ; CHECK-FISL-DAG: xsmaddasp 4, 2, 3 107 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 12 108 ; CHECK-FISL-DAG: stxsspx 4, 8, [[C1]] 109 ; CHECK-FISL-DAG: xsmaddasp 1, 2, 5 110 ; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8 111 ; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]] 112 ; CHECK-FISL-DAG: li [[C3:[0-9]+]], 4 113 ; CHECK-FISL-DAG: stxsspx 0, 8, [[C3]] 114 ; CHECK-FISL: blr 115 } 116 117 define void @test4sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 { 118 entry: 119 %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a) 120 store float %0, float* %d, align 4 121 %1 = tail call float @llvm.fma.f32(float %b, float %e, float %a) 122 %arrayidx1 = getelementptr inbounds float, float* %d, i64 1 123 store float %1, float* %arrayidx1, align 4 124 %2 = tail call float @llvm.fma.f32(float %b, float %c, float %1) 125 %arrayidx3 = getelementptr inbounds float, float* %d, i64 3 126 store float %2, float* %arrayidx3, align 4 127 %3 = tail call float @llvm.fma.f32(float %b, float %f, float %a) 128 %arrayidx4 = getelementptr inbounds float, float* %d, i64 2 129 store float %3, float* %arrayidx4, align 4 130 ret void 131 132 ; CHECK-LABEL: @test4sp 133 ; CHECK-DAG: fmr [[F1:[0-9]+]], 1 134 ; CHECK-DAG: li [[C1:[0-9]+]], 4 135 ; CHECK-DAG: li [[C2:[0-9]+]], 8 136 ; CHECK-DAG: xsmaddmsp 4, 2, 1 137 138 ; Note: We could convert this next FMA to M-type as well, but it would require 139 ; re-ordering the instructions. 140 ; CHECK-DAG: xsmaddasp 1, 2, 5 141 142 ; CHECK-DAG: xsmaddasp [[F1]], 2, 3 143 ; CHECK-DAG: stxsspx [[F1]], 0, 8 144 ; CHECK-DAG: stxsspx 4, 8, [[C1]] 145 ; CHECK-DAG: li [[C3:[0-9]+]], 12 146 ; CHECK-DAG: xsmaddasp 4, 2, 3 147 ; CHECK-DAG: stxsspx 4, 8, [[C3]] 148 ; CHECK-DAG: stxsspx 1, 8, [[C2]] 149 ; CHECK: blr 150 151 ; CHECK-FISL-LABEL: @test4sp 152 ; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1 153 ; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 3 154 ; CHECK-FISL-DAG: stxsspx 0, 0, 8 155 ; CHECK-FISL-DAG: fmr [[F1]], 1 156 ; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 4 157 ; CHECK-FISL-DAG: li [[C3:[0-9]+]], 4 158 ; CHECK-FISL-DAG: stxsspx 0, 8, [[C3]] 159 ; CHECK-FISL-DAG: xsmaddasp 0, 2, 3 160 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 12 161 ; CHECK-FISL-DAG: stxsspx 0, 8, [[C1]] 162 ; CHECK-FISL-DAG: xsmaddasp 1, 2, 5 163 ; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8 164 ; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]] 165 ; CHECK-FISL: blr 166 } 167 168 declare float @llvm.fma.f32(float, float, float) #0 169
