1 ; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck %s 2 ; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck -check-prefix=CHECK-REG %s 3 ; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck %s 4 ; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s 5 target datalayout = "E-m:e-i64:64-n32:64" 6 target triple = "powerpc64-unknown-linux-gnu" 7 8 ; Unaligned loads/stores on P8 and later should use VSX where possible. 9 10 define <2 x double> @test28u(<2 x double>* %a) { 11 %v = load <2 x double>, <2 x double>* %a, align 8 12 ret <2 x double> %v 13 14 ; CHECK-LABEL: @test28u 15 ; CHECK: lxvd2x 34, 0, 3 16 ; CHECK: blr 17 } 18 19 define void @test29u(<2 x double>* %a, <2 x double> %b) { 20 store <2 x double> %b, <2 x double>* %a, align 8 21 ret void 22 23 ; CHECK-LABEL: @test29u 24 ; CHECK: stxvd2x 34, 0, 3 25 ; CHECK: blr 26 } 27 28 define <4 x float> @test32u(<4 x float>* %a) { 29 %v = load <4 x float>, <4 x float>* %a, align 8 30 ret <4 x float> %v 31 32 ; CHECK-REG-LABEL: @test32u 33 ; CHECK-REG: lxvw4x 34, 0, 3 34 ; CHECK-REG: blr 35 36 ; CHECK-FISL-LABEL: @test32u 37 ; CHECK-FISL: lxvw4x 0, 0, 3 38 ; CHECK-FISL: xxlor 34, 0, 0 39 ; CHECK-FISL: blr 40 } 41 42 define void @test33u(<4 x float>* %a, <4 x float> %b) { 43 store <4 x float> %b, <4 x float>* %a, align 8 44 ret void 45 46 ; CHECK-REG-LABEL: @test33u 47 ; CHECK-REG: stxvw4x 34, 0, 3 48 ; CHECK-REG: blr 49 50 ; CHECK-FISL-LABEL: @test33u 51 ; CHECK-FISL: vor 3, 2, 2 52 ; CHECK-FISL: stxvw4x 35, 0, 3 53 ; CHECK-FISL: blr 54 } 55 56
