1 ; RUN: llc < %s 2 ; PR6372 3 ; 4 ; This test produces a move instruction with an implicitly defined super-register: 5 ; 6 ; %DL<def> = MOV8rr %reg1038<kill>, %RDX<imp-def> 7 ; 8 ; When %DL is rematerialized, we must remember to update live intervals for 9 ; sub-registers %DX and %EDX. 10 11 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" 12 target triple = "x86_64-apple-darwin10.0.0" 13 14 define noalias i8* @foo() nounwind ssp { 15 entry: 16 br i1 undef, label %for.end, label %for.body 17 18 for.body: ; preds = %if.end40, %entry 19 %tmp6 = load i8, i8* undef, align 2 ; <i8> [#uses=3] 20 %conv11 = sext i8 %tmp6 to i64 ; <i64> [#uses=1] 21 %cmp15 = icmp slt i64 %conv11, undef ; <i1> [#uses=1] 22 br i1 %cmp15, label %if.end, label %if.then 23 24 if.then: ; preds = %for.body 25 %conv18 = sext i8 %tmp6 to i32 ; <i32> [#uses=1] 26 %call = tail call i32 (...) @invalid(i32 0, i32 0, i32 %conv18) nounwind ; <i32> [#uses=0] 27 br label %if.end 28 29 if.end: ; preds = %if.then, %for.body 30 %index.0 = phi i8 [ 0, %if.then ], [ %tmp6, %for.body ] ; <i8> [#uses=1] 31 store i8 %index.0, i8* undef 32 %tmp24 = load i8, i8* undef ; <i8> [#uses=2] 33 br i1 undef, label %if.end40, label %if.then36 34 35 if.then36: ; preds = %if.end 36 %conv38 = sext i8 %tmp24 to i32 ; <i32> [#uses=1] 37 %call39 = tail call i32 (...) @invalid(i32 0, i32 0, i32 %conv38) nounwind ; <i32> [#uses=0] 38 br label %if.end40 39 40 if.end40: ; preds = %if.then36, %if.end 41 %index.1 = phi i8 [ 0, %if.then36 ], [ %tmp24, %if.end ] ; <i8> [#uses=1] 42 store i8 %index.1, i8* undef 43 br i1 false, label %for.body, label %for.end 44 45 for.end: ; preds = %if.end40, %entry 46 ret i8* undef 47 } 48 49 declare i32 @invalid(...) 50
