1 ; Tests for SSE1 and below, without SSE2+. 2 ; RUN: llc < %s -mtriple=i386-unknown-unknown -march=x86 -mcpu=pentium3 -O3 | FileCheck %s 3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mattr=-sse2,+sse -O3 | FileCheck %s 4 5 ; PR7993 6 ;define <4 x i32> @test3(<4 x i16> %a) nounwind { 7 ; %c = sext <4 x i16> %a to <4 x i32> ; <<4 x i32>> [#uses=1] 8 ; ret <4 x i32> %c 9 ;} 10 11 ; This should not emit shuffles to populate the top 2 elements of the 4-element 12 ; vector that this ends up returning. 13 ; rdar://8368414 14 define <2 x float> @test4(<2 x float> %A, <2 x float> %B) nounwind { 15 ; CHECK-LABEL: test4: 16 ; CHECK: # BB#0: # %entry 17 ; CHECK-NEXT: movaps %xmm0, %xmm2 18 ; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3] 19 ; CHECK-NEXT: addss %xmm1, %xmm0 20 ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3] 21 ; CHECK-NEXT: subss %xmm1, %xmm2 22 ; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] 23 ; CHECK-NEXT: ret 24 entry: 25 %tmp7 = extractelement <2 x float> %A, i32 0 26 %tmp5 = extractelement <2 x float> %A, i32 1 27 %tmp3 = extractelement <2 x float> %B, i32 0 28 %tmp1 = extractelement <2 x float> %B, i32 1 29 %add.r = fadd float %tmp7, %tmp3 30 %add.i = fsub float %tmp5, %tmp1 31 %tmp11 = insertelement <2 x float> undef, float %add.r, i32 0 32 %tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1 33 ret <2 x float> %tmp9 34 } 35 36 ; We used to get stuck in type legalization for this example when lowering the 37 ; vselect. With SSE1 v4f32 is a legal type but v4i1 (or any vector integer type) 38 ; is not. We used to ping pong between splitting the vselect for the v4i 39 ; condition operand and widening the resulting vselect for the v4f32 result. 40 ; PR18036 41 42 define <4 x float> @vselect(<4 x float>*%p, <4 x i32> %q) { 43 ; CHECK-LABEL: vselect: 44 ; CHECK: ret 45 entry: 46 %a1 = icmp eq <4 x i32> %q, zeroinitializer 47 %a14 = select <4 x i1> %a1, <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+0> , <4 x float> zeroinitializer 48 ret <4 x float> %a14 49 } 50
