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      1 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse4.1 | FileCheck %s
      2 ; This test works just like the non-upgrade one except that it only checks
      3 ; forms which require auto-upgrading.
      4 
      5 define <2 x double> @test_x86_sse41_blendpd(<2 x double> %a0, <2 x double> %a1) {
      6   ; CHECK: blendpd
      7   %res = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i32 7) ; <<2 x double>> [#uses=1]
      8   ret <2 x double> %res
      9 }
     10 declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i32) nounwind readnone
     11 
     12 
     13 define <4 x float> @test_x86_sse41_blendps(<4 x float> %a0, <4 x float> %a1) {
     14   ; CHECK: blendps
     15   %res = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]
     16   ret <4 x float> %res
     17 }
     18 declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i32) nounwind readnone
     19 
     20 
     21 define <2 x double> @test_x86_sse41_dppd(<2 x double> %a0, <2 x double> %a1) {
     22   ; CHECK: dppd
     23   %res = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i32 7) ; <<2 x double>> [#uses=1]
     24   ret <2 x double> %res
     25 }
     26 declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i32) nounwind readnone
     27 
     28 
     29 define <4 x float> @test_x86_sse41_dpps(<4 x float> %a0, <4 x float> %a1) {
     30   ; CHECK: dpps
     31   %res = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]
     32   ret <4 x float> %res
     33 }
     34 declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i32) nounwind readnone
     35 
     36 
     37 define <4 x float> @test_x86_sse41_insertps(<4 x float> %a0, <4 x float> %a1) {
     38   ; CHECK: insertps
     39   %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]
     40   ret <4 x float> %res
     41 }
     42 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
     43 
     44 
     45 define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
     46   ; CHECK: mpsadbw
     47   %res = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i32 7) ; <<8 x i16>> [#uses=1]
     48   ret <8 x i16> %res
     49 }
     50 declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i32) nounwind readnone
     51 
     52 
     53 define <8 x i16> @test_x86_sse41_pblendw(<8 x i16> %a0, <8 x i16> %a1) {
     54   ; CHECK: pblendw
     55   %res = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i32 7) ; <<8 x i16>> [#uses=1]
     56   ret <8 x i16> %res
     57 }
     58 declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i32) nounwind readnone
     59 
     60 
     61 define <4 x i32> @test_x86_sse41_pmovsxbd(<16 x i8> %a0) {
     62   ; CHECK: pmovsxbd
     63   %res = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %a0) ; <<4 x i32>> [#uses=1]
     64   ret <4 x i32> %res
     65 }
     66 declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
     67 
     68 
     69 define <2 x i64> @test_x86_sse41_pmovsxbq(<16 x i8> %a0) {
     70   ; CHECK: pmovsxbq
     71   %res = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %a0) ; <<2 x i64>> [#uses=1]
     72   ret <2 x i64> %res
     73 }
     74 declare <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8>) nounwind readnone
     75 
     76 
     77 define <8 x i16> @test_x86_sse41_pmovsxbw(<16 x i8> %a0) {
     78   ; CHECK: pmovsxbw
     79   %res = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1]
     80   ret <8 x i16> %res
     81 }
     82 declare <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8>) nounwind readnone
     83 
     84 
     85 define <2 x i64> @test_x86_sse41_pmovsxdq(<4 x i32> %a0) {
     86   ; CHECK: pmovsxdq
     87   %res = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %a0) ; <<2 x i64>> [#uses=1]
     88   ret <2 x i64> %res
     89 }
     90 declare <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32>) nounwind readnone
     91 
     92 
     93 define <4 x i32> @test_x86_sse41_pmovsxwd(<8 x i16> %a0) {
     94   ; CHECK: pmovsxwd
     95   %res = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %a0) ; <<4 x i32>> [#uses=1]
     96   ret <4 x i32> %res
     97 }
     98 declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
     99 
    100 
    101 define <2 x i64> @test_x86_sse41_pmovsxwq(<8 x i16> %a0) {
    102   ; CHECK: pmovsxwq
    103   %res = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %a0) ; <<2 x i64>> [#uses=1]
    104   ret <2 x i64> %res
    105 }
    106 declare <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16>) nounwind readnone
    107