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      1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s
      2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s
      3 
      4 define <2 x double> @fabs_v2f64(<2 x double> %p)
      5 {
      6   ; CHECK-LABEL: fabs_v2f64
      7   ; CHECK: vandpd
      8   %t = call <2 x double> @llvm.fabs.v2f64(<2 x double> %p)
      9   ret <2 x double> %t
     10 }
     11 declare <2 x double> @llvm.fabs.v2f64(<2 x double> %p)
     12 
     13 define <4 x float> @fabs_v4f32(<4 x float> %p)
     14 {
     15   ; CHECK-LABEL: fabs_v4f32
     16   ; CHECK: vandps
     17   %t = call <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
     18   ret <4 x float> %t
     19 }
     20 declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
     21 
     22 define <4 x double> @fabs_v4f64(<4 x double> %p)
     23 {
     24   ; CHECK-LABEL: fabs_v4f64
     25   ; CHECK: vandpd
     26   %t = call <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
     27   ret <4 x double> %t
     28 }
     29 declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
     30 
     31 define <8 x float> @fabs_v8f32(<8 x float> %p)
     32 {
     33   ; CHECK-LABEL: fabs_v8f32
     34   ; CHECK: vandps
     35   %t = call <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
     36   ret <8 x float> %t
     37 }
     38 declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
     39 
     40 ; PR20354: when generating code for a vector fabs op,
     41 ; make sure that we're only turning off the sign bit of each float value.
     42 ; No constant pool loads or vector ops are needed for the fabs of a
     43 ; bitcasted integer constant; we should just return an integer constant
     44 ; that has the sign bits turned off.
     45 ;
     46 ; So instead of something like this:
     47 ;    movabsq (constant pool load of mask for sign bits) 
     48 ;    vmovq   (move from integer register to vector/fp register)
     49 ;    vandps  (mask off sign bits)
     50 ;    vmovq   (move vector/fp register back to integer return register)
     51 ;
     52 ; We should generate:
     53 ;    mov     (put constant value in return register)
     54 
     55 define i64 @fabs_v2f32_1() {
     56 ; CHECK-LABEL: fabs_v2f32_1:
     57 ; CHECK: movabsq $9223372032559808512, %rax # imm = 0x7FFFFFFF00000000
     58 ; CHECK-NEXT: retq
     59  %bitcast = bitcast i64 18446744069414584320 to <2 x float> ; 0xFFFF_FFFF_0000_0000
     60  %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %bitcast)
     61  %ret = bitcast <2 x float> %fabs to i64
     62  ret i64 %ret
     63 }
     64 
     65 define i64 @fabs_v2f32_2() {
     66 ; CHECK-LABEL: fabs_v2f32_2:
     67 ; CHECK: movl $2147483647, %eax       # imm = 0x7FFFFFFF
     68 ; CHECK-NEXT: retq
     69  %bitcast = bitcast i64 4294967295 to <2 x float> ; 0x0000_0000_FFFF_FFFF
     70  %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %bitcast)
     71  %ret = bitcast <2 x float> %fabs to i64
     72  ret i64 %ret
     73 }
     74 
     75 declare <2 x float> @llvm.fabs.v2f32(<2 x float> %p)
     76