1 ; RUN: opt < %s -instcombine -S | FileCheck %s 2 3 declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>) nounwind readnone 4 declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone 5 declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>) nounwind readnone 6 declare <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32>) nounwind readnone 7 declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone 8 declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>) nounwind readnone 9 10 declare <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8>) nounwind readnone 11 declare <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8>) nounwind readnone 12 declare <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8>) nounwind readnone 13 declare <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32>) nounwind readnone 14 declare <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16>) nounwind readnone 15 declare <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16>) nounwind readnone 16 17 ; 18 ; Basic zero extension tests 19 ; 20 21 define <4 x i32> @sse41_pmovzxbd(<16 x i8> %v) nounwind readnone { 22 ; CHECK-LABEL: @sse41_pmovzxbd 23 ; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 24 ; CHECK-NEXT: zext <4 x i8> %1 to <4 x i32> 25 ; CHECK-NEXT: ret <4 x i32> %2 26 27 %res = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %v) 28 ret <4 x i32> %res 29 } 30 31 define <2 x i64> @sse41_pmovzxbq(<16 x i8> %v) nounwind readnone { 32 ; CHECK-LABEL: @sse41_pmovzxbq 33 ; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <2 x i32> <i32 0, i32 1> 34 ; CHECK-NEXT: zext <2 x i8> %1 to <2 x i64> 35 ; CHECK-NEXT: ret <2 x i64> %2 36 37 %res = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %v) 38 ret <2 x i64> %res 39 } 40 41 define <8 x i16> @sse41_pmovzxbw(<16 x i8> %v) nounwind readnone { 42 ; CHECK-LABEL: @sse41_pmovzxbw 43 ; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 44 ; CHECK-NEXT: zext <8 x i8> %1 to <8 x i16> 45 ; CHECK-NEXT: ret <8 x i16> %2 46 47 %res = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %v) 48 ret <8 x i16> %res 49 } 50 51 define <2 x i64> @sse41_pmovzxdq(<4 x i32> %v) nounwind readnone { 52 ; CHECK-LABEL: @sse41_pmovzxdq 53 ; CHECK-NEXT: shufflevector <4 x i32> %v, <4 x i32> undef, <2 x i32> <i32 0, i32 1> 54 ; CHECK-NEXT: zext <2 x i32> %1 to <2 x i64> 55 ; CHECK-NEXT: ret <2 x i64> %2 56 57 %res = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %v) 58 ret <2 x i64> %res 59 } 60 61 define <4 x i32> @sse41_pmovzxwd(<8 x i16> %v) nounwind readnone { 62 ; CHECK-LABEL: @sse41_pmovzxwd 63 ; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 64 ; CHECK-NEXT: zext <4 x i16> %1 to <4 x i32> 65 ; CHECK-NEXT: ret <4 x i32> %2 66 67 %res = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %v) 68 ret <4 x i32> %res 69 } 70 71 define <2 x i64> @sse41_pmovzxwq(<8 x i16> %v) nounwind readnone { 72 ; CHECK-LABEL: @sse41_pmovzxwq 73 ; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <2 x i32> <i32 0, i32 1> 74 ; CHECK-NEXT: zext <2 x i16> %1 to <2 x i64> 75 ; CHECK-NEXT: ret <2 x i64> %2 76 77 %res = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %v) 78 ret <2 x i64> %res 79 } 80 81 define <8 x i32> @avx2_pmovzxbd(<16 x i8> %v) nounwind readnone { 82 ; CHECK-LABEL: @avx2_pmovzxbd 83 ; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 84 ; CHECK-NEXT: zext <8 x i8> %1 to <8 x i32> 85 ; CHECK-NEXT: ret <8 x i32> %2 86 87 %res = call <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8> %v) 88 ret <8 x i32> %res 89 } 90 91 define <4 x i64> @avx2_pmovzxbq(<16 x i8> %v) nounwind readnone { 92 ; CHECK-LABEL: @avx2_pmovzxbq 93 ; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 94 ; CHECK-NEXT: zext <4 x i8> %1 to <4 x i64> 95 ; CHECK-NEXT: ret <4 x i64> %2 96 97 %res = call <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8> %v) 98 ret <4 x i64> %res 99 } 100 101 define <16 x i16> @avx2_pmovzxbw(<16 x i8> %v) nounwind readnone { 102 ; CHECK-LABEL: @avx2_pmovzxbw 103 ; CHECK-NEXT: zext <16 x i8> %v to <16 x i16> 104 ; CHECK-NEXT: ret <16 x i16> %1 105 106 %res = call <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8> %v) 107 ret <16 x i16> %res 108 } 109 110 define <4 x i64> @avx2_pmovzxdq(<4 x i32> %v) nounwind readnone { 111 ; CHECK-LABEL: @avx2_pmovzxdq 112 ; CHECK-NEXT: zext <4 x i32> %v to <4 x i64> 113 ; CHECK-NEXT: ret <4 x i64> %1 114 115 %res = call <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32> %v) 116 ret <4 x i64> %res 117 } 118 119 define <8 x i32> @avx2_pmovzxwd(<8 x i16> %v) nounwind readnone { 120 ; CHECK-LABEL: @avx2_pmovzxwd 121 ; CHECK-NEXT: zext <8 x i16> %v to <8 x i32> 122 ; CHECK-NEXT: ret <8 x i32> %1 123 124 %res = call <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16> %v) 125 ret <8 x i32> %res 126 } 127 128 define <4 x i64> @avx2_pmovzxwq(<8 x i16> %v) nounwind readnone { 129 ; CHECK-LABEL: @avx2_pmovzxwq 130 ; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 131 ; CHECK-NEXT: zext <4 x i16> %1 to <4 x i64> 132 ; CHECK-NEXT: ret <4 x i64> %2 133 134 %res = call <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16> %v) 135 ret <4 x i64> %res 136 } 137
