1 ; RUN: opt < %s -loop-reduce -S | FileCheck %s 2 3 target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" 4 target triple = "nvptx64-nvidia-cuda" 5 6 ; This confirms that NVPTXTTI considers a 64-to-32 integer trunc free. If such 7 ; truncs were not considered free, LSR would promote (int)i as a separate 8 ; induction variable in the following example. 9 ; 10 ; for (long i = begin; i != end; i += stride) 11 ; use((int)i); 12 ; 13 ; That would be worthless, because "i" is simulated by two 32-bit registers and 14 ; truncating it to 32-bit is as simple as directly using the register that 15 ; contains the low bits. 16 define void @trunc_is_free(i64 %begin, i64 %stride, i64 %end) { 17 ; CHECK-LABEL: @trunc_is_free( 18 entry: 19 %cmp.4 = icmp eq i64 %begin, %end 20 br i1 %cmp.4, label %for.cond.cleanup, label %for.body.preheader 21 22 for.body.preheader: ; preds = %entry 23 br label %for.body 24 25 for.cond.cleanup.loopexit: ; preds = %for.body 26 br label %for.cond.cleanup 27 28 for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry 29 ret void 30 31 for.body: ; preds = %for.body.preheader, %for.body 32 ; CHECK: for.body: 33 %i.05 = phi i64 [ %add, %for.body ], [ %begin, %for.body.preheader ] 34 %conv = trunc i64 %i.05 to i32 35 ; CHECK: trunc i64 %{{[^ ]+}} to i32 36 tail call void @_Z3usei(i32 %conv) #2 37 %add = add nsw i64 %i.05, %stride 38 %cmp = icmp eq i64 %add, %end 39 br i1 %cmp, label %for.cond.cleanup.loopexit, label %for.body 40 } 41 42 declare void @_Z3usei(i32) 43 44 !nvvm.annotations = !{!0} 45 !0 = !{void (i64, i64, i64)* @trunc_is_free, !"kernel", i32 1} 46
