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      1 ; RUN: opt < %s  -basicaa -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -dce -instcombine -S -enable-if-conversion | FileCheck %s
      2 
      3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
      4 target triple = "x86_64-apple-macosx10.8.0"
      5 
      6 @A = global [36 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35], align 16
      7 @B = global [36 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35], align 16
      8 
      9 ;CHECK-LABEL:@_Z5test1v(
     10 ;CHECK: load <4 x i32>
     11 ;CHECK: shufflevector <4 x i32>
     12 ;CHECK: store <4 x i32>
     13 ;CHECK: ret
     14 define i32 @_Z5test1v() nounwind uwtable ssp {
     15   br label %1
     16 
     17 ; <label>:1                                       ; preds = %0, %1
     18   %p.02 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @A, i64 0, i64 18), %0 ], [ %4, %1 ]
     19   %b.01 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @B, i64 0, i64 0), %0 ], [ %5, %1 ]
     20   %2 = load i32, i32* %b.01, align 4
     21   %3 = shl nsw i32 %2, 1
     22   store i32 %3, i32* %p.02, align 4
     23   %4 = getelementptr inbounds i32, i32* %p.02, i64 -1
     24   %5 = getelementptr inbounds i32, i32* %b.01, i64 1
     25   %6 = icmp eq i32* %4, getelementptr ([36 x i32], [36 x i32]* @A, i64 128102389400760775, i64 3)
     26   br i1 %6, label %7, label %1
     27 
     28 ; <label>:7                                       ; preds = %1
     29   ret i32 0
     30 }
     31 
     32 ;CHECK-LABEL: @_Z5test2v(
     33 ;CHECK: load <4 x i32>
     34 ;CHECK: shufflevector <4 x i32>
     35 ;CHECK: store <4 x i32>
     36 ;CHECK: ret
     37 define i32 @_Z5test2v() nounwind uwtable ssp {
     38   br label %1
     39 
     40 ; <label>:1                                       ; preds = %0, %1
     41   %p.02 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @A, i64 0, i64 25), %0 ], [ %3, %1 ]
     42   %b.01 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @B, i64 0, i64 2), %0 ], [ %4, %1 ]
     43   %2 = load i32, i32* %b.01, align 4
     44   store i32 %2, i32* %p.02, align 4
     45   %3 = getelementptr inbounds i32, i32* %p.02, i64 -1
     46   %4 = getelementptr inbounds i32, i32* %b.01, i64 1
     47   %5 = icmp eq i32* %4, getelementptr inbounds ([36 x i32], [36 x i32]* @A, i64 0, i64 18)
     48   br i1 %5, label %6, label %1
     49 
     50 ; <label>:6                                       ; preds = %1
     51   ret i32 0
     52 }
     53 
     54 ;CHECK:_Z5test3v
     55 ;CHECK: load <4 x i32>
     56 ;CHECK: shufflevector <4 x i32>
     57 ;CHECK: store <4 x i32>
     58 ;CHECK: ret
     59 define i32 @_Z5test3v() nounwind uwtable ssp {
     60   br label %1
     61 
     62 ; <label>:1                                       ; preds = %0, %1
     63   %p.02 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @A, i64 0, i64 29), %0 ], [ %3, %1 ]
     64   %b.01 = phi i32* [ getelementptr inbounds ([36 x i32], [36 x i32]* @B, i64 0, i64 5), %0 ], [ %4, %1 ]
     65   %2 = load i32, i32* %b.01, align 4
     66   store i32 %2, i32* %p.02, align 4
     67   %3 = getelementptr inbounds i32, i32* %p.02, i64 -1
     68   %4 = getelementptr inbounds i32, i32* %b.01, i64 1
     69   %5 = icmp eq i32* %3, getelementptr ([36 x i32], [36 x i32]* @A, i64 128102389400760775, i64 3)
     70   br i1 %5, label %6, label %1
     71 
     72 ; <label>:6                                       ; preds = %1
     73   ret i32 0
     74 }
     75