1 // Copyright 2010 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 // This module gets enough CPU information to optimize the 6 // atomicops module on x86. 7 8 #include <string.h> // NOLINT(build/include) 9 10 #include "src/base/atomicops.h" 11 12 // This file only makes sense with atomicops_internals_x86_gcc.h -- it 13 // depends on structs that are defined in that file. If atomicops.h 14 // doesn't sub-include that file, then we aren't needed, and shouldn't 15 // try to do anything. 16 #ifdef V8_BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ 17 18 // Inline cpuid instruction. In PIC compilations, %ebx contains the address 19 // of the global offset table. To avoid breaking such executables, this code 20 // must preserve that register's value across cpuid instructions. 21 #if defined(__i386__) 22 #define cpuid(a, b, c, d, inp) \ 23 asm("mov %%ebx, %%edi\n" \ 24 "cpuid\n" \ 25 "xchg %%edi, %%ebx\n" \ 26 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) 27 #elif defined(__x86_64__) 28 #define cpuid(a, b, c, d, inp) \ 29 asm("mov %%rbx, %%rdi\n" \ 30 "cpuid\n" \ 31 "xchg %%rdi, %%rbx\n" \ 32 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) 33 #endif 34 35 #if defined(cpuid) // initialize the struct only on x86 36 37 namespace v8 { 38 namespace base { 39 40 // Set the flags so that code will run correctly and conservatively, so even 41 // if we haven't been initialized yet, we're probably single threaded, and our 42 // default values should hopefully be pretty safe. 43 struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = { 44 false, // bug can't exist before process spawns multiple threads 45 #if !defined(__SSE2__) 46 false, // no SSE2 47 #endif 48 }; 49 50 } // namespace base 51 } // namespace v8 52 53 namespace { 54 55 // Initialize the AtomicOps_Internalx86CPUFeatures struct. 56 void AtomicOps_Internalx86CPUFeaturesInit() { 57 using v8::base::AtomicOps_Internalx86CPUFeatures; 58 59 uint32_t eax = 0; 60 uint32_t ebx = 0; 61 uint32_t ecx = 0; 62 uint32_t edx = 0; 63 64 // Get vendor string (issue CPUID with eax = 0) 65 cpuid(eax, ebx, ecx, edx, 0); 66 char vendor[13]; 67 memcpy(vendor, &ebx, 4); 68 memcpy(vendor + 4, &edx, 4); 69 memcpy(vendor + 8, &ecx, 4); 70 vendor[12] = 0; 71 72 // get feature flags in ecx/edx, and family/model in eax 73 cpuid(eax, ebx, ecx, edx, 1); 74 75 int family = (eax >> 8) & 0xf; // family and model fields 76 int model = (eax >> 4) & 0xf; 77 if (family == 0xf) { // use extended family and model fields 78 family += (eax >> 20) & 0xff; 79 model += ((eax >> 16) & 0xf) << 4; 80 } 81 82 // Opteron Rev E has a bug in which on very rare occasions a locked 83 // instruction doesn't act as a read-acquire barrier if followed by a 84 // non-locked read-modify-write instruction. Rev F has this bug in 85 // pre-release versions, but not in versions released to customers, 86 // so we test only for Rev E, which is family 15, model 32..63 inclusive. 87 if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD 88 family == 15 && 89 32 <= model && model <= 63) { 90 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true; 91 } else { 92 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false; 93 } 94 95 #if !defined(__SSE2__) 96 // edx bit 26 is SSE2 which we use to tell use whether we can use mfence 97 AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1); 98 #endif 99 } 100 101 class AtomicOpsx86Initializer { 102 public: 103 AtomicOpsx86Initializer() { 104 AtomicOps_Internalx86CPUFeaturesInit(); 105 } 106 }; 107 108 109 // A global to get use initialized on startup via static initialization :/ 110 AtomicOpsx86Initializer g_initer; 111 112 } // namespace 113 114 #endif // if x86 115 116 #endif // ifdef V8_BASE_ATOMICOPS_INTERNALS_X86_GCC_H_ 117
