1 2 /*---------------------------------------------------------------*/ 3 /*--- begin host_tilegx_defs.h ---*/ 4 /*---------------------------------------------------------------*/ 5 6 /* 7 This file is part of Valgrind, a dynamic binary instrumentation 8 framework. 9 10 Copyright (C) 2010-2015 Tilera Corp. 11 12 This program is free software; you can redistribute it and/or 13 modify it under the terms of the GNU General Public License as 14 published by the Free Software Foundation; either version 2 of the 15 License, or (at your option) any later version. 16 17 This program is distributed in the hope that it will be useful, but 18 WITHOUT ANY WARRANTY; without even the implied warranty of 19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 General Public License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with this program; if not, write to the Free Software 24 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 25 02111-1307, USA. 26 27 The GNU General Public License is contained in the file COPYING. 28 */ 29 30 /* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */ 31 32 #ifndef __VEX_HOST_TILEGX_DEFS_H 33 #define __VEX_HOST_TILEGX_DEFS_H 34 35 #include "tilegx_disasm.h" 36 37 /* Num registers used for function calls */ 38 #define TILEGX_N_REGPARMS 10 39 40 /* --------- Registers. --------- */ 41 42 /* The usual HReg abstraction. 43 There are 56 general purpose regs. 44 */ 45 46 #define ST_IN static inline 47 48 ST_IN HReg hregTILEGX_R30 ( void ) { return mkHReg(False, HRcInt64, 30, 0); } 49 ST_IN HReg hregTILEGX_R31 ( void ) { return mkHReg(False, HRcInt64, 31, 1); } 50 ST_IN HReg hregTILEGX_R32 ( void ) { return mkHReg(False, HRcInt64, 32, 2); } 51 ST_IN HReg hregTILEGX_R33 ( void ) { return mkHReg(False, HRcInt64, 33, 3); } 52 ST_IN HReg hregTILEGX_R34 ( void ) { return mkHReg(False, HRcInt64, 34, 4); } 53 ST_IN HReg hregTILEGX_R35 ( void ) { return mkHReg(False, HRcInt64, 35, 5); } 54 ST_IN HReg hregTILEGX_R36 ( void ) { return mkHReg(False, HRcInt64, 36, 6); } 55 ST_IN HReg hregTILEGX_R37 ( void ) { return mkHReg(False, HRcInt64, 37, 7); } 56 ST_IN HReg hregTILEGX_R38 ( void ) { return mkHReg(False, HRcInt64, 38, 8); } 57 ST_IN HReg hregTILEGX_R39 ( void ) { return mkHReg(False, HRcInt64, 39, 9); } 58 59 ST_IN HReg hregTILEGX_R40 ( void ) { return mkHReg(False, HRcInt64, 40, 10); } 60 ST_IN HReg hregTILEGX_R41 ( void ) { return mkHReg(False, HRcInt64, 41, 11); } 61 ST_IN HReg hregTILEGX_R42 ( void ) { return mkHReg(False, HRcInt64, 42, 12); } 62 ST_IN HReg hregTILEGX_R43 ( void ) { return mkHReg(False, HRcInt64, 43, 13); } 63 ST_IN HReg hregTILEGX_R44 ( void ) { return mkHReg(False, HRcInt64, 44, 14); } 64 ST_IN HReg hregTILEGX_R45 ( void ) { return mkHReg(False, HRcInt64, 45, 15); } 65 ST_IN HReg hregTILEGX_R46 ( void ) { return mkHReg(False, HRcInt64, 46, 16); } 66 ST_IN HReg hregTILEGX_R47 ( void ) { return mkHReg(False, HRcInt64, 47, 17); } 67 ST_IN HReg hregTILEGX_R48 ( void ) { return mkHReg(False, HRcInt64, 48, 18); } 68 ST_IN HReg hregTILEGX_R49 ( void ) { return mkHReg(False, HRcInt64, 49, 19); } 69 70 ST_IN HReg hregTILEGX_R10 ( void ) { return mkHReg(False, HRcInt64, 10, 20); } 71 ST_IN HReg hregTILEGX_R13 ( void ) { return mkHReg(False, HRcInt64, 13, 21); } 72 ST_IN HReg hregTILEGX_R14 ( void ) { return mkHReg(False, HRcInt64, 14, 22); } 73 ST_IN HReg hregTILEGX_R15 ( void ) { return mkHReg(False, HRcInt64, 15, 23); } 74 ST_IN HReg hregTILEGX_R16 ( void ) { return mkHReg(False, HRcInt64, 16, 24); } 75 ST_IN HReg hregTILEGX_R17 ( void ) { return mkHReg(False, HRcInt64, 17, 25); } 76 ST_IN HReg hregTILEGX_R18 ( void ) { return mkHReg(False, HRcInt64, 18, 26); } 77 ST_IN HReg hregTILEGX_R19 ( void ) { return mkHReg(False, HRcInt64, 19, 27); } 78 ST_IN HReg hregTILEGX_R20 ( void ) { return mkHReg(False, HRcInt64, 20, 28); } 79 80 ST_IN HReg hregTILEGX_R21 ( void ) { return mkHReg(False, HRcInt64, 21, 29); } 81 ST_IN HReg hregTILEGX_R22 ( void ) { return mkHReg(False, HRcInt64, 22, 30); } 82 ST_IN HReg hregTILEGX_R23 ( void ) { return mkHReg(False, HRcInt64, 23, 31); } 83 ST_IN HReg hregTILEGX_R24 ( void ) { return mkHReg(False, HRcInt64, 24, 32); } 84 ST_IN HReg hregTILEGX_R25 ( void ) { return mkHReg(False, HRcInt64, 25, 33); } 85 ST_IN HReg hregTILEGX_R26 ( void ) { return mkHReg(False, HRcInt64, 26, 34); } 86 ST_IN HReg hregTILEGX_R27 ( void ) { return mkHReg(False, HRcInt64, 27, 35); } 87 ST_IN HReg hregTILEGX_R28 ( void ) { return mkHReg(False, HRcInt64, 28, 36); } 88 ST_IN HReg hregTILEGX_R29 ( void ) { return mkHReg(False, HRcInt64, 29, 37); } 89 90 ST_IN HReg hregTILEGX_R0 ( void ) { return mkHReg(False, HRcInt64, 0, 38); } 91 ST_IN HReg hregTILEGX_R1 ( void ) { return mkHReg(False, HRcInt64, 1, 39); } 92 ST_IN HReg hregTILEGX_R2 ( void ) { return mkHReg(False, HRcInt64, 2, 40); } 93 ST_IN HReg hregTILEGX_R3 ( void ) { return mkHReg(False, HRcInt64, 3, 41); } 94 ST_IN HReg hregTILEGX_R4 ( void ) { return mkHReg(False, HRcInt64, 4, 42); } 95 ST_IN HReg hregTILEGX_R5 ( void ) { return mkHReg(False, HRcInt64, 5, 43); } 96 ST_IN HReg hregTILEGX_R6 ( void ) { return mkHReg(False, HRcInt64, 6, 44); } 97 ST_IN HReg hregTILEGX_R7 ( void ) { return mkHReg(False, HRcInt64, 7, 45); } 98 ST_IN HReg hregTILEGX_R8 ( void ) { return mkHReg(False, HRcInt64, 8, 46); } 99 ST_IN HReg hregTILEGX_R9 ( void ) { return mkHReg(False, HRcInt64, 9, 47); } 100 101 ST_IN HReg hregTILEGX_R11 ( void ) { return mkHReg(False, HRcInt64, 11, 48); } 102 ST_IN HReg hregTILEGX_R12 ( void ) { return mkHReg(False, HRcInt64, 12, 49); } 103 ST_IN HReg hregTILEGX_R50 ( void ) { return mkHReg(False, HRcInt64, 50, 50); } 104 ST_IN HReg hregTILEGX_R51 ( void ) { return mkHReg(False, HRcInt64, 51, 51); } 105 ST_IN HReg hregTILEGX_R52 ( void ) { return mkHReg(False, HRcInt64, 52, 52); } 106 ST_IN HReg hregTILEGX_R53 ( void ) { return mkHReg(False, HRcInt64, 53, 53); } 107 ST_IN HReg hregTILEGX_R54 ( void ) { return mkHReg(False, HRcInt64, 54, 54); } 108 ST_IN HReg hregTILEGX_R55 ( void ) { return mkHReg(False, HRcInt64, 55, 55); } 109 ST_IN HReg hregTILEGX_R63 ( void ) { return mkHReg(False, HRcInt64, 63, 56); } 110 111 extern void ppHRegTILEGX ( HReg ); 112 113 #define TILEGXGuestStatePointer() hregTILEGX_R50() 114 #define TILEGXStackFramePointer() hregTILEGX_R52() 115 #define TILEGXLinkRegister() hregTILEGX_R55() 116 #define TILEGXStackPointer() hregTILEGX_R54() 117 118 /* r0, r1, r2, r3 ... r9 */ 119 #define TILEGX_N_ARGREGS 10 120 121 /* --------- Condition codes, Tilegx encoding. --------- */ 122 typedef enum { 123 TILEGXcc_EQ = 0, /* equal */ 124 TILEGXcc_NE = 1, /* not equal */ 125 TILEGXcc_HS = 2, /* >=u (higher or same) */ 126 TILEGXcc_LO = 3, /* <u (lower) */ 127 TILEGXcc_MI = 4, /* minus (negative) */ 128 TILEGXcc_PL = 5, /* plus (zero or +ve) */ 129 TILEGXcc_VS = 6, /* overflow */ 130 TILEGXcc_VC = 7, /* no overflow */ 131 TILEGXcc_HI = 8, /* >u (higher) */ 132 TILEGXcc_LS = 9, /* <=u (lower or same) */ 133 TILEGXcc_GE = 10, /* >=s (signed greater or equal) */ 134 TILEGXcc_LT = 11, /* <s (signed less than) */ 135 TILEGXcc_GT = 12, /* >s (signed greater) */ 136 TILEGXcc_LE = 13, /* <=s (signed less or equal) */ 137 TILEGXcc_AL = 14, /* always (unconditional) */ 138 TILEGXcc_NV = 15, /* never (unconditional): */ 139 TILEGXcc_EQ8x8 = 16,/* V1 equal */ 140 TILEGXcc_NE8x8 = 17,/* V1 not equal */ 141 TILEGXcc_EZ = 18, /* equal 0 */ 142 TILEGXcc_NZ = 19, /* not equal */ 143 144 } TILEGXCondCode; 145 146 /* --------- Memory address expressions (amodes). --------- */ 147 typedef enum { 148 GXam_IR, /* Immediate (signed 16-bit) + Reg */ 149 } TILEGXAModeTag; 150 151 typedef struct { 152 TILEGXAModeTag tag; 153 union { 154 struct { 155 HReg base; 156 Int index; 157 } IR; 158 struct { 159 HReg base; 160 HReg index; 161 } RR; 162 } GXam; 163 } TILEGXAMode; 164 165 extern TILEGXAMode *TILEGXAMode_IR ( Int, HReg ); 166 extern TILEGXAMode *TILEGXAMode_RR ( HReg, HReg ); 167 extern TILEGXAMode *dopyTILEGXAMode ( TILEGXAMode * ); 168 extern TILEGXAMode *nextTILEGXAModeFloat ( TILEGXAMode * ); 169 extern TILEGXAMode *nextTILEGXAModeInt ( TILEGXAMode * ); 170 extern void ppTILEGXAMode ( const TILEGXAMode * ); 171 172 /* --------- Operand, which can be a reg or a u16/s16. --------- */ 173 /* ("RH" == "Register or Halfword immediate") */ 174 typedef enum { 175 GXrh_Imm, 176 GXrh_Reg 177 } TILEGXRHTag; 178 179 typedef struct { 180 TILEGXRHTag tag; 181 union { 182 struct { 183 Bool syned; 184 UShort imm16; 185 } Imm; 186 struct { 187 HReg reg; 188 } Reg; 189 } GXrh; 190 } TILEGXRH; 191 192 extern void ppTILEGXRH ( const TILEGXRH * ); 193 extern TILEGXRH *TILEGXRH_Imm ( Bool, UShort ); 194 extern TILEGXRH *TILEGXRH_Reg ( HReg ); 195 196 /* --------- Reg or imm5 operands --------- */ 197 typedef enum { 198 TILEGXri5_I5 = 7, /* imm5, 1 .. 31 only (no zero!) */ 199 TILEGXri5_R /* reg */ 200 } TILEGXRI5Tag; 201 202 typedef struct { 203 TILEGXRI5Tag tag; 204 union { 205 struct { 206 UInt imm5; 207 } I5; 208 struct { 209 HReg reg; 210 } R; 211 } TILEGXri5; 212 } TILEGXRI5; 213 214 extern TILEGXRI5 *TILEGXRI5_I5 ( UInt imm5 ); 215 extern TILEGXRI5 *TILEGXRI5_R ( HReg ); 216 217 extern void ppTILEGXRI5 ( const TILEGXRI5 * ); 218 219 /* --------- Instructions. --------- */ 220 221 /*Tags for operations*/ 222 223 /* --------- */ 224 typedef enum { 225 GXun_CLZ, 226 GXun_CTZ, 227 GXun_NOP, 228 } TILEGXUnaryOp; 229 230 /* --------- */ 231 232 typedef enum { 233 GXalu_INVALID, 234 GXalu_ADD, 235 GXalu_SUB, 236 GXalu_AND, 237 GXalu_OR, 238 GXalu_NOR, 239 GXalu_XOR, 240 } TILEGXAluOp; 241 242 /* --------- */ 243 244 typedef enum { 245 GXshft_INVALID, 246 GXshft_SLL, 247 GXshft_SRL, 248 GXshft_SRA, 249 GXshft_SLL8x8, 250 GXshft_SRL8x8, 251 252 } TILEGXShftOp; 253 254 255 /* --------- */ 256 typedef enum { 257 GXbf_EXTS, 258 GXbf_EXTU, 259 GXbf_INS 260 } TILEGXBfOp; 261 262 /* --------- */ 263 264 265 /* --------- */ 266 typedef enum { 267 GXacas_CMPEXCH, 268 GXacas_EXCH, 269 GXacas_FetchAnd, 270 GXacas_FetchAdd, 271 GXacas_FetchAddgez, 272 GXacas_FetchOr, 273 } TILEGXAcasOp; 274 275 /* --------- */ 276 277 /* ----- Instruction tags ----- */ 278 typedef enum { 279 GXin_LI, /* load word (32/64-bit) immediate (fake insn) */ 280 GXin_Alu, /* word add/sub/and/or/xor/nor/others? */ 281 GXin_Shft, /* word sll/srl/sra */ 282 GXin_Unary, /* clo, clz, nop, neg */ 283 284 GXin_Cmp, /* word compare (fake insn) */ 285 GXin_CmpI, 286 287 GXin_Mul, /* widening/non-widening multiply */ 288 289 GXin_Call, /* call to address in register */ 290 291 GXin_XDirect, /* direct transfer to GA */ 292 GXin_XIndir, /* indirect transfer to GA */ 293 GXin_XAssisted, /* assisted transfer to GA */ 294 GXin_EvCheck, /* Event check */ 295 GXin_ProfInc, /* 64-bit profile counter increment */ 296 297 GXin_RdWrLR, /* Read/Write Link Register */ 298 299 GXin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */ 300 GXin_Store, /* store a 8|16|32|64 bit value to mem */ 301 302 GXin_MovCond, 303 GXin_Bf, /* Bitfield operations */ 304 GXin_Acas, /* Atomic Campare and swap. */ 305 306 } TILEGXInstrTag; 307 308 /*--------- Structure for instructions ----------*/ 309 /* Destinations are on the LEFT (first operand) */ 310 311 typedef struct { 312 TILEGXInstrTag tag; 313 union { 314 /* Get a 32/64-bit literal into a register. 315 May turn into a number of real insns. */ 316 struct { 317 HReg dst; 318 ULong imm; 319 } LI; 320 /* Integer add/sub/and/or/xor. Limitations: 321 - For add, the immediate, if it exists, is a signed 16. 322 - For sub, the immediate, if it exists, is a signed 16 323 which may not be -32768, since no such instruction 324 exists, and so we have to emit addi with +32768, but 325 that is not possible. 326 - For and/or/xor, the immediate, if it exists, 327 is an unsigned 16. 328 */ 329 struct { 330 TILEGXAluOp op; 331 HReg dst; 332 HReg srcL; 333 TILEGXRH *srcR; 334 } Alu; 335 336 struct { 337 TILEGXBfOp op; 338 HReg dst; 339 HReg src; 340 UInt Start; 341 UInt End; 342 } Bf; 343 344 struct { 345 TILEGXAcasOp op; 346 HReg addr; 347 HReg exp; 348 HReg new; 349 HReg old; 350 UInt sz; 351 } Acas; 352 353 /* Integer shl/shr/sar. 354 Limitations: the immediate, if it exists, 355 is a signed 5-bit value between 1 and 31 inclusive. 356 */ 357 struct { 358 TILEGXShftOp op; 359 Bool sz32; 360 HReg dst; 361 HReg srcL; 362 TILEGXRH *srcR; 363 } Shft; 364 /* Clz, Ctz, Clo, nop */ 365 struct { 366 TILEGXUnaryOp op; 367 HReg dst; 368 HReg src; 369 } Unary; 370 /* Word compare. Fake instruction, used for basic block ending */ 371 struct { 372 Bool syned; 373 Bool sz32; 374 HReg dst; 375 HReg srcL; 376 HReg srcR; 377 TILEGXCondCode cond; 378 } Cmp; 379 struct { 380 Bool syned; 381 Bool sz32; 382 HReg dst; 383 HReg srcL; 384 TILEGXRH *srcR; 385 TILEGXCondCode cond; 386 } CmpI; 387 struct { 388 Bool widening; //True => widening, False => non-widening 389 Bool syned; //signed/unsigned - meaningless if widenind = False 390 Bool sz32; 391 HReg dst; 392 HReg srcL; 393 HReg srcR; 394 } Mul; 395 /* Pseudo-insn. Call target (an absolute address), on given 396 condition (which could be Mcc_ALWAYS). argiregs indicates 397 which of r0 .. r9 398 carries argument values for this call, 399 using a bit mask (1<<N is set if rN holds an arg, for N in 400 0 .. 9 inclusive). 401 If cond is != Mcc_ALWAYS, src is checked. 402 Otherwise, unconditional call */ 403 struct { 404 TILEGXCondCode cond; 405 Addr64 target; 406 ULong argiregs; 407 HReg src; 408 RetLoc rloc; /* where the return value saved. */ 409 } Call; 410 411 /* Update the guest IP value, then exit requesting to chain 412 to it. May be conditional. Urr, use of Addr32 implicitly 413 assumes that wordsize(guest) == wordsize(host). */ 414 struct { 415 Addr64 dstGA; /* next guest address */ 416 TILEGXAMode* amPC; /* amode in guest state for PC */ 417 TILEGXCondCode cond; /* can be TILEGXcc_AL */ 418 Bool toFastEP; /* chain to the slow or fast point? */ 419 } XDirect; 420 421 /* Boring transfer to a guest address not known at JIT time. 422 Not chainable. May be conditional. */ 423 struct { 424 HReg dstGA; 425 TILEGXAMode* amPC; 426 TILEGXCondCode cond; /* can be TILEGXcc_AL */ 427 } XIndir; 428 429 /* Assisted transfer to a guest address, most general case. 430 Not chainable. May be conditional. */ 431 struct { 432 HReg dstGA; 433 TILEGXAMode* amPC; 434 TILEGXCondCode cond; /* can be TILEGXcc_AL */ 435 IRJumpKind jk; 436 } XAssisted; 437 438 struct { 439 TILEGXAMode* amCounter; 440 TILEGXAMode* amFailAddr; 441 } EvCheck; 442 443 struct { 444 /* No fields. The address of the counter to inc is 445 installed later, post-translation, by patching it in, 446 as it is not known at translation time. */ 447 } ProfInc; 448 /* Zero extending loads. Dst size is host word size */ 449 struct { 450 UChar sz; /* 1|2|4|8 */ 451 HReg dst; 452 TILEGXAMode *src; 453 } Load; 454 /* 64/32/16/8 bit stores */ 455 struct { 456 UChar sz; /* 1|2|4|8 */ 457 TILEGXAMode *dst; 458 HReg src; 459 } Store; 460 /* Read/Write Link Register */ 461 struct { 462 Bool wrLR; 463 HReg gpr; 464 } RdWrLR; 465 struct { 466 HReg dst; 467 HReg srcL; 468 TILEGXRH *srcR; 469 HReg condR; 470 TILEGXCondCode cond; 471 } MovCond; 472 } GXin; 473 } TILEGXInstr; 474 extern TILEGXInstr *TILEGXInstr_LI ( HReg, ULong ); 475 extern TILEGXInstr *TILEGXInstr_Alu ( TILEGXAluOp, HReg, HReg, TILEGXRH * ); 476 extern TILEGXInstr *TILEGXInstr_Shft ( TILEGXShftOp, Bool sz32, HReg, HReg, 477 TILEGXRH * ); 478 extern TILEGXInstr *TILEGXInstr_Unary ( TILEGXUnaryOp op, HReg dst, HReg src ); 479 extern TILEGXInstr *TILEGXInstr_Cmp ( Bool, Bool, HReg, HReg, HReg, 480 TILEGXCondCode ); 481 extern TILEGXInstr *TILEGXInstr_CmpI ( Bool, Bool, HReg, HReg, TILEGXRH *, 482 TILEGXCondCode ); 483 extern TILEGXInstr *TILEGXInstr_Bf ( TILEGXBfOp op, HReg dst, HReg src, 484 UInt Start, UInt End ); 485 extern TILEGXInstr *TILEGXInstr_Acas ( TILEGXAcasOp op, HReg old, HReg addr, 486 HReg exp, HReg new, UInt sz ); 487 extern TILEGXInstr *TILEGXInstr_Mul ( Bool syned, Bool hi32, Bool sz32, HReg, 488 HReg, HReg ); 489 extern TILEGXInstr *TILEGXInstr_Div ( Bool syned, Bool sz32, HReg, HReg ); 490 extern TILEGXInstr *TILEGXInstr_Madd ( Bool, HReg, HReg ); 491 extern TILEGXInstr *TILEGXInstr_Msub ( Bool, HReg, HReg ); 492 493 extern TILEGXInstr *TILEGXInstr_Load ( UChar sz, HReg dst, TILEGXAMode * src ); 494 495 extern TILEGXInstr *TILEGXInstr_Store ( UChar sz, TILEGXAMode * dst, HReg src ); 496 497 extern TILEGXInstr *TILEGXInstr_LoadL ( UChar sz, HReg dst, TILEGXAMode * src ); 498 499 extern TILEGXInstr *TILEGXInstr_StoreC ( UChar sz, TILEGXAMode * dst, HReg src ); 500 501 extern TILEGXInstr *TILEGXInstr_Call ( TILEGXCondCode, Addr64, ULong, HReg ); 502 extern TILEGXInstr *TILEGXInstr_CallAlways ( TILEGXCondCode, Addr64, ULong ); 503 extern TILEGXInstr *TILEGXInstr_XDirect ( Addr64 dstGA, TILEGXAMode* amPC, 504 TILEGXCondCode cond, Bool toFastEP ); 505 extern TILEGXInstr *TILEGXInstr_XIndir ( HReg dstGA, TILEGXAMode* amPC, 506 TILEGXCondCode cond ); 507 extern TILEGXInstr *TILEGXInstr_XAssisted ( HReg dstGA, TILEGXAMode* amPC, 508 TILEGXCondCode cond, IRJumpKind jk ); 509 extern TILEGXInstr *TILEGXInstr_EvCheck ( TILEGXAMode* amCounter, 510 TILEGXAMode* amFailAddr ); 511 extern TILEGXInstr* TILEGXInstr_ProfInc (void); 512 513 extern TILEGXInstr *TILEGXInstr_Goto ( IRJumpKind, TILEGXCondCode, 514 TILEGXRH * dst, HReg ); 515 extern TILEGXInstr *TILEGXInstr_GotoAlways ( IRJumpKind, TILEGXRH * ); 516 extern TILEGXInstr *TILEGXInstr_RdWrLR ( Bool wrLR, HReg gpr ); 517 extern TILEGXInstr *TILEGXInstr_MovCond ( HReg dst, HReg srcL, TILEGXRH * src, 518 HReg condR, TILEGXCondCode cond ); 519 extern void ppTILEGXInstr ( const TILEGXInstr * ); 520 521 /* Some functions that insulate the register allocator from details 522 of the underlying instruction set. */ 523 extern void getRegUsage_TILEGXInstr ( HRegUsage *, TILEGXInstr *); 524 extern void mapRegs_TILEGXInstr ( HRegRemap *, TILEGXInstr *); 525 extern Bool isMove_TILEGXInstr ( TILEGXInstr *, HReg *, HReg * ); 526 extern Int emit_TILEGXInstr ( Bool*, UChar*, Int, TILEGXInstr*, Bool, VexEndness, 527 void*, void*, void*, void* ); 528 extern void genSpill_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, 529 HReg rreg, Int offset ); 530 extern void genReload_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, 531 HReg rreg, Int offset ); 532 533 extern const RRegUniverse* getRRegUniverse_TILEGX ( void ); 534 535 extern HInstrArray *iselSB_TILEGX ( const IRSB*, VexArch, 536 const VexArchInfo*, 537 const VexAbiInfo*, 538 Int, Int, Bool, Bool, Addr); 539 extern const HChar *showTILEGXCondCode ( TILEGXCondCode cond ); 540 extern Int evCheckSzB_TILEGX (void); 541 extern VexInvalRange chainXDirect_TILEGX ( VexEndness endness_host, 542 void* place_to_chain, 543 const void* disp_cp_chain_me_EXPECTED, 544 const void* place_to_jump_to, 545 Bool mode64 ); 546 extern VexInvalRange unchainXDirect_TILEGX ( VexEndness endness_host, 547 void* place_to_unchain, 548 const void* place_to_jump_to_EXPECTED, 549 const void* disp_cp_chain_me, 550 Bool mode64 ); 551 extern VexInvalRange patchProfInc_TILEGX ( VexEndness endness_host, 552 void* place_to_patch, 553 const ULong* location_of_counter, 554 Bool mode64 ); 555 556 extern Int decode_and_display ( tilegx_bundle_bits *p, Int count, ULong pc ); 557 558 #endif /* __LIBVEX_HOST_TILEGX_HDEFS_H */ 559 560 /*---------------------------------------------------------------*/ 561 /*--- end host-tilegx_defs.h ---*/ 562 /*---------------------------------------------------------------*/ 563
