1 // Copyright 2014 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 package ppc64 6 7 import ( 8 "cmd/compile/internal/gc" 9 "cmd/internal/obj" 10 "cmd/internal/obj/ppc64" 11 ) 12 13 const ( 14 LeftRdwr uint32 = gc.LeftRead | gc.LeftWrite 15 RightRdwr uint32 = gc.RightRead | gc.RightWrite 16 ) 17 18 // This table gives the basic information about instruction 19 // generated by the compiler and processed in the optimizer. 20 // See opt.h for bit definitions. 21 // 22 // Instructions not generated need not be listed. 23 // As an exception to that rule, we typically write down all the 24 // size variants of an operation even if we just use a subset. 25 // 26 // The table is formatted for 8-space tabs. 27 var progtable = [ppc64.ALAST]obj.ProgInfo{ 28 obj.ATYPE: {gc.Pseudo | gc.Skip, 0, 0, 0}, 29 obj.ATEXT: {gc.Pseudo, 0, 0, 0}, 30 obj.AFUNCDATA: {gc.Pseudo, 0, 0, 0}, 31 obj.APCDATA: {gc.Pseudo, 0, 0, 0}, 32 obj.AUNDEF: {gc.Break, 0, 0, 0}, 33 obj.AUSEFIELD: {gc.OK, 0, 0, 0}, 34 obj.ACHECKNIL: {gc.LeftRead, 0, 0, 0}, 35 obj.AVARDEF: {gc.Pseudo | gc.RightWrite, 0, 0, 0}, 36 obj.AVARKILL: {gc.Pseudo | gc.RightWrite, 0, 0, 0}, 37 38 // NOP is an internal no-op that also stands 39 // for USED and SET annotations, not the Power opcode. 40 obj.ANOP: {gc.LeftRead | gc.RightWrite, 0, 0, 0}, 41 42 // Integer 43 ppc64.AADD: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 44 ppc64.ASUB: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 45 ppc64.ANEG: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 46 ppc64.AAND: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 47 ppc64.AOR: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 48 ppc64.AXOR: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 49 ppc64.AMULLD: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 50 ppc64.AMULLW: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 51 ppc64.AMULHD: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 52 ppc64.AMULHDU: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 53 ppc64.ADIVD: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 54 ppc64.ADIVDU: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 55 ppc64.ASLD: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 56 ppc64.ASRD: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 57 ppc64.ASRAD: {gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 58 ppc64.ACMP: {gc.SizeQ | gc.LeftRead | gc.RightRead, 0, 0, 0}, 59 ppc64.ACMPU: {gc.SizeQ | gc.LeftRead | gc.RightRead, 0, 0, 0}, 60 ppc64.ATD: {gc.SizeQ | gc.RightRead, 0, 0, 0}, 61 62 // Floating point. 63 ppc64.AFADD: {gc.SizeD | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 64 ppc64.AFADDS: {gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 65 ppc64.AFSUB: {gc.SizeD | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 66 ppc64.AFSUBS: {gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 67 ppc64.AFMUL: {gc.SizeD | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 68 ppc64.AFMULS: {gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 69 ppc64.AFDIV: {gc.SizeD | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 70 ppc64.AFDIVS: {gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 71 ppc64.AFCTIDZ: {gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 72 ppc64.AFCFID: {gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0}, 73 ppc64.AFCMPU: {gc.SizeD | gc.LeftRead | gc.RightRead, 0, 0, 0}, 74 ppc64.AFRSP: {gc.SizeD | gc.LeftRead | gc.RightWrite | gc.Conv, 0, 0, 0}, 75 76 // Moves 77 ppc64.AMOVB: {gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv, 0, 0, 0}, 78 ppc64.AMOVBU: {gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv | gc.PostInc, 0, 0, 0}, 79 ppc64.AMOVBZ: {gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv, 0, 0, 0}, 80 ppc64.AMOVH: {gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv, 0, 0, 0}, 81 ppc64.AMOVHU: {gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv | gc.PostInc, 0, 0, 0}, 82 ppc64.AMOVHZ: {gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv, 0, 0, 0}, 83 ppc64.AMOVW: {gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv, 0, 0, 0}, 84 85 // there is no AMOVWU. 86 ppc64.AMOVWZU: {gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv | gc.PostInc, 0, 0, 0}, 87 ppc64.AMOVWZ: {gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv, 0, 0, 0}, 88 ppc64.AMOVD: {gc.SizeQ | gc.LeftRead | gc.RightWrite | gc.Move, 0, 0, 0}, 89 ppc64.AMOVDU: {gc.SizeQ | gc.LeftRead | gc.RightWrite | gc.Move | gc.PostInc, 0, 0, 0}, 90 ppc64.AFMOVS: {gc.SizeF | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv, 0, 0, 0}, 91 ppc64.AFMOVD: {gc.SizeD | gc.LeftRead | gc.RightWrite | gc.Move, 0, 0, 0}, 92 93 // Jumps 94 ppc64.ABR: {gc.Jump | gc.Break, 0, 0, 0}, 95 ppc64.ABL: {gc.Call, 0, 0, 0}, 96 ppc64.ABEQ: {gc.Cjmp, 0, 0, 0}, 97 ppc64.ABNE: {gc.Cjmp, 0, 0, 0}, 98 ppc64.ABGE: {gc.Cjmp, 0, 0, 0}, 99 ppc64.ABLT: {gc.Cjmp, 0, 0, 0}, 100 ppc64.ABGT: {gc.Cjmp, 0, 0, 0}, 101 ppc64.ABLE: {gc.Cjmp, 0, 0, 0}, 102 obj.ARET: {gc.Break, 0, 0, 0}, 103 obj.ADUFFZERO: {gc.Call, 0, 0, 0}, 104 obj.ADUFFCOPY: {gc.Call, 0, 0, 0}, 105 } 106 107 var initproginfo_initialized int 108 109 func initproginfo() { 110 var addvariant = []int{V_CC, V_V, V_CC | V_V} 111 112 if initproginfo_initialized != 0 { 113 return 114 } 115 initproginfo_initialized = 1 116 117 // Perform one-time expansion of instructions in progtable to 118 // their CC, V, and VCC variants 119 var as2 int 120 var i int 121 var variant int 122 for as := int(0); as < len(progtable); as++ { 123 if progtable[as].Flags == 0 { 124 continue 125 } 126 variant = as2variant(as) 127 for i = 0; i < len(addvariant); i++ { 128 as2 = variant2as(as, variant|addvariant[i]) 129 if as2 != 0 && progtable[as2].Flags == 0 { 130 progtable[as2] = progtable[as] 131 } 132 } 133 } 134 } 135 136 func proginfo(p *obj.Prog) { 137 initproginfo() 138 139 info := &p.Info 140 *info = progtable[p.As] 141 if info.Flags == 0 { 142 gc.Fatal("proginfo: unknown instruction %v", p) 143 } 144 145 if (info.Flags&gc.RegRead != 0) && p.Reg == 0 { 146 info.Flags &^= gc.RegRead 147 info.Flags |= gc.RightRead /*CanRegRead |*/ 148 } 149 150 if (p.From.Type == obj.TYPE_MEM || p.From.Type == obj.TYPE_ADDR) && p.From.Reg != 0 { 151 info.Regindex |= RtoB(int(p.From.Reg)) 152 if info.Flags&gc.PostInc != 0 { 153 info.Regset |= RtoB(int(p.From.Reg)) 154 } 155 } 156 157 if (p.To.Type == obj.TYPE_MEM || p.To.Type == obj.TYPE_ADDR) && p.To.Reg != 0 { 158 info.Regindex |= RtoB(int(p.To.Reg)) 159 if info.Flags&gc.PostInc != 0 { 160 info.Regset |= RtoB(int(p.To.Reg)) 161 } 162 } 163 164 if p.From.Type == obj.TYPE_ADDR && p.From.Sym != nil && (info.Flags&gc.LeftRead != 0) { 165 info.Flags &^= gc.LeftRead 166 info.Flags |= gc.LeftAddr 167 } 168 169 if p.As == obj.ADUFFZERO { 170 info.Reguse |= 1<<0 | RtoB(ppc64.REG_R3) 171 info.Regset |= RtoB(ppc64.REG_R3) 172 } 173 174 if p.As == obj.ADUFFCOPY { 175 // TODO(austin) Revisit when duffcopy is implemented 176 info.Reguse |= RtoB(ppc64.REG_R3) | RtoB(ppc64.REG_R4) | RtoB(ppc64.REG_R5) 177 178 info.Regset |= RtoB(ppc64.REG_R3) | RtoB(ppc64.REG_R4) 179 } 180 } 181 182 // Instruction variants table. Initially this contains entries only 183 // for the "base" form of each instruction. On the first call to 184 // as2variant or variant2as, we'll add the variants to the table. 185 var varianttable = [ppc64.ALAST][4]int{ 186 ppc64.AADD: [4]int{ppc64.AADD, ppc64.AADDCC, ppc64.AADDV, ppc64.AADDVCC}, 187 ppc64.AADDC: [4]int{ppc64.AADDC, ppc64.AADDCCC, ppc64.AADDCV, ppc64.AADDCVCC}, 188 ppc64.AADDE: [4]int{ppc64.AADDE, ppc64.AADDECC, ppc64.AADDEV, ppc64.AADDEVCC}, 189 ppc64.AADDME: [4]int{ppc64.AADDME, ppc64.AADDMECC, ppc64.AADDMEV, ppc64.AADDMEVCC}, 190 ppc64.AADDZE: [4]int{ppc64.AADDZE, ppc64.AADDZECC, ppc64.AADDZEV, ppc64.AADDZEVCC}, 191 ppc64.AAND: [4]int{ppc64.AAND, ppc64.AANDCC, 0, 0}, 192 ppc64.AANDN: [4]int{ppc64.AANDN, ppc64.AANDNCC, 0, 0}, 193 ppc64.ACNTLZD: [4]int{ppc64.ACNTLZD, ppc64.ACNTLZDCC, 0, 0}, 194 ppc64.ACNTLZW: [4]int{ppc64.ACNTLZW, ppc64.ACNTLZWCC, 0, 0}, 195 ppc64.ADIVD: [4]int{ppc64.ADIVD, ppc64.ADIVDCC, ppc64.ADIVDV, ppc64.ADIVDVCC}, 196 ppc64.ADIVDU: [4]int{ppc64.ADIVDU, ppc64.ADIVDUCC, ppc64.ADIVDUV, ppc64.ADIVDUVCC}, 197 ppc64.ADIVW: [4]int{ppc64.ADIVW, ppc64.ADIVWCC, ppc64.ADIVWV, ppc64.ADIVWVCC}, 198 ppc64.ADIVWU: [4]int{ppc64.ADIVWU, ppc64.ADIVWUCC, ppc64.ADIVWUV, ppc64.ADIVWUVCC}, 199 ppc64.AEQV: [4]int{ppc64.AEQV, ppc64.AEQVCC, 0, 0}, 200 ppc64.AEXTSB: [4]int{ppc64.AEXTSB, ppc64.AEXTSBCC, 0, 0}, 201 ppc64.AEXTSH: [4]int{ppc64.AEXTSH, ppc64.AEXTSHCC, 0, 0}, 202 ppc64.AEXTSW: [4]int{ppc64.AEXTSW, ppc64.AEXTSWCC, 0, 0}, 203 ppc64.AFABS: [4]int{ppc64.AFABS, ppc64.AFABSCC, 0, 0}, 204 ppc64.AFADD: [4]int{ppc64.AFADD, ppc64.AFADDCC, 0, 0}, 205 ppc64.AFADDS: [4]int{ppc64.AFADDS, ppc64.AFADDSCC, 0, 0}, 206 ppc64.AFCFID: [4]int{ppc64.AFCFID, ppc64.AFCFIDCC, 0, 0}, 207 ppc64.AFCTID: [4]int{ppc64.AFCTID, ppc64.AFCTIDCC, 0, 0}, 208 ppc64.AFCTIDZ: [4]int{ppc64.AFCTIDZ, ppc64.AFCTIDZCC, 0, 0}, 209 ppc64.AFCTIW: [4]int{ppc64.AFCTIW, ppc64.AFCTIWCC, 0, 0}, 210 ppc64.AFCTIWZ: [4]int{ppc64.AFCTIWZ, ppc64.AFCTIWZCC, 0, 0}, 211 ppc64.AFDIV: [4]int{ppc64.AFDIV, ppc64.AFDIVCC, 0, 0}, 212 ppc64.AFDIVS: [4]int{ppc64.AFDIVS, ppc64.AFDIVSCC, 0, 0}, 213 ppc64.AFMADD: [4]int{ppc64.AFMADD, ppc64.AFMADDCC, 0, 0}, 214 ppc64.AFMADDS: [4]int{ppc64.AFMADDS, ppc64.AFMADDSCC, 0, 0}, 215 ppc64.AFMOVD: [4]int{ppc64.AFMOVD, ppc64.AFMOVDCC, 0, 0}, 216 ppc64.AFMSUB: [4]int{ppc64.AFMSUB, ppc64.AFMSUBCC, 0, 0}, 217 ppc64.AFMSUBS: [4]int{ppc64.AFMSUBS, ppc64.AFMSUBSCC, 0, 0}, 218 ppc64.AFMUL: [4]int{ppc64.AFMUL, ppc64.AFMULCC, 0, 0}, 219 ppc64.AFMULS: [4]int{ppc64.AFMULS, ppc64.AFMULSCC, 0, 0}, 220 ppc64.AFNABS: [4]int{ppc64.AFNABS, ppc64.AFNABSCC, 0, 0}, 221 ppc64.AFNEG: [4]int{ppc64.AFNEG, ppc64.AFNEGCC, 0, 0}, 222 ppc64.AFNMADD: [4]int{ppc64.AFNMADD, ppc64.AFNMADDCC, 0, 0}, 223 ppc64.AFNMADDS: [4]int{ppc64.AFNMADDS, ppc64.AFNMADDSCC, 0, 0}, 224 ppc64.AFNMSUB: [4]int{ppc64.AFNMSUB, ppc64.AFNMSUBCC, 0, 0}, 225 ppc64.AFNMSUBS: [4]int{ppc64.AFNMSUBS, ppc64.AFNMSUBSCC, 0, 0}, 226 ppc64.AFRES: [4]int{ppc64.AFRES, ppc64.AFRESCC, 0, 0}, 227 ppc64.AFRSP: [4]int{ppc64.AFRSP, ppc64.AFRSPCC, 0, 0}, 228 ppc64.AFRSQRTE: [4]int{ppc64.AFRSQRTE, ppc64.AFRSQRTECC, 0, 0}, 229 ppc64.AFSEL: [4]int{ppc64.AFSEL, ppc64.AFSELCC, 0, 0}, 230 ppc64.AFSQRT: [4]int{ppc64.AFSQRT, ppc64.AFSQRTCC, 0, 0}, 231 ppc64.AFSQRTS: [4]int{ppc64.AFSQRTS, ppc64.AFSQRTSCC, 0, 0}, 232 ppc64.AFSUB: [4]int{ppc64.AFSUB, ppc64.AFSUBCC, 0, 0}, 233 ppc64.AFSUBS: [4]int{ppc64.AFSUBS, ppc64.AFSUBSCC, 0, 0}, 234 ppc64.AMTFSB0: [4]int{ppc64.AMTFSB0, ppc64.AMTFSB0CC, 0, 0}, 235 ppc64.AMTFSB1: [4]int{ppc64.AMTFSB1, ppc64.AMTFSB1CC, 0, 0}, 236 ppc64.AMULHD: [4]int{ppc64.AMULHD, ppc64.AMULHDCC, 0, 0}, 237 ppc64.AMULHDU: [4]int{ppc64.AMULHDU, ppc64.AMULHDUCC, 0, 0}, 238 ppc64.AMULHW: [4]int{ppc64.AMULHW, ppc64.AMULHWCC, 0, 0}, 239 ppc64.AMULHWU: [4]int{ppc64.AMULHWU, ppc64.AMULHWUCC, 0, 0}, 240 ppc64.AMULLD: [4]int{ppc64.AMULLD, ppc64.AMULLDCC, ppc64.AMULLDV, ppc64.AMULLDVCC}, 241 ppc64.AMULLW: [4]int{ppc64.AMULLW, ppc64.AMULLWCC, ppc64.AMULLWV, ppc64.AMULLWVCC}, 242 ppc64.ANAND: [4]int{ppc64.ANAND, ppc64.ANANDCC, 0, 0}, 243 ppc64.ANEG: [4]int{ppc64.ANEG, ppc64.ANEGCC, ppc64.ANEGV, ppc64.ANEGVCC}, 244 ppc64.ANOR: [4]int{ppc64.ANOR, ppc64.ANORCC, 0, 0}, 245 ppc64.AOR: [4]int{ppc64.AOR, ppc64.AORCC, 0, 0}, 246 ppc64.AORN: [4]int{ppc64.AORN, ppc64.AORNCC, 0, 0}, 247 ppc64.AREM: [4]int{ppc64.AREM, ppc64.AREMCC, ppc64.AREMV, ppc64.AREMVCC}, 248 ppc64.AREMD: [4]int{ppc64.AREMD, ppc64.AREMDCC, ppc64.AREMDV, ppc64.AREMDVCC}, 249 ppc64.AREMDU: [4]int{ppc64.AREMDU, ppc64.AREMDUCC, ppc64.AREMDUV, ppc64.AREMDUVCC}, 250 ppc64.AREMU: [4]int{ppc64.AREMU, ppc64.AREMUCC, ppc64.AREMUV, ppc64.AREMUVCC}, 251 ppc64.ARLDC: [4]int{ppc64.ARLDC, ppc64.ARLDCCC, 0, 0}, 252 ppc64.ARLDCL: [4]int{ppc64.ARLDCL, ppc64.ARLDCLCC, 0, 0}, 253 ppc64.ARLDCR: [4]int{ppc64.ARLDCR, ppc64.ARLDCRCC, 0, 0}, 254 ppc64.ARLDMI: [4]int{ppc64.ARLDMI, ppc64.ARLDMICC, 0, 0}, 255 ppc64.ARLWMI: [4]int{ppc64.ARLWMI, ppc64.ARLWMICC, 0, 0}, 256 ppc64.ARLWNM: [4]int{ppc64.ARLWNM, ppc64.ARLWNMCC, 0, 0}, 257 ppc64.ASLD: [4]int{ppc64.ASLD, ppc64.ASLDCC, 0, 0}, 258 ppc64.ASLW: [4]int{ppc64.ASLW, ppc64.ASLWCC, 0, 0}, 259 ppc64.ASRAD: [4]int{ppc64.ASRAD, ppc64.ASRADCC, 0, 0}, 260 ppc64.ASRAW: [4]int{ppc64.ASRAW, ppc64.ASRAWCC, 0, 0}, 261 ppc64.ASRD: [4]int{ppc64.ASRD, ppc64.ASRDCC, 0, 0}, 262 ppc64.ASRW: [4]int{ppc64.ASRW, ppc64.ASRWCC, 0, 0}, 263 ppc64.ASUB: [4]int{ppc64.ASUB, ppc64.ASUBCC, ppc64.ASUBV, ppc64.ASUBVCC}, 264 ppc64.ASUBC: [4]int{ppc64.ASUBC, ppc64.ASUBCCC, ppc64.ASUBCV, ppc64.ASUBCVCC}, 265 ppc64.ASUBE: [4]int{ppc64.ASUBE, ppc64.ASUBECC, ppc64.ASUBEV, ppc64.ASUBEVCC}, 266 ppc64.ASUBME: [4]int{ppc64.ASUBME, ppc64.ASUBMECC, ppc64.ASUBMEV, ppc64.ASUBMEVCC}, 267 ppc64.ASUBZE: [4]int{ppc64.ASUBZE, ppc64.ASUBZECC, ppc64.ASUBZEV, ppc64.ASUBZEVCC}, 268 ppc64.AXOR: [4]int{ppc64.AXOR, ppc64.AXORCC, 0, 0}, 269 } 270 271 var initvariants_initialized int 272 273 func initvariants() { 274 if initvariants_initialized != 0 { 275 return 276 } 277 initvariants_initialized = 1 278 279 var j int 280 for i := int(0); i < len(varianttable); i++ { 281 if varianttable[i][0] == 0 { 282 // Instruction has no variants 283 varianttable[i][0] = i 284 285 continue 286 } 287 288 // Copy base form to other variants 289 if varianttable[i][0] == i { 290 for j = 0; j < len(varianttable[i]); j++ { 291 varianttable[varianttable[i][j]] = varianttable[i] 292 } 293 } 294 } 295 } 296 297 // as2variant returns the variant (V_*) flags of instruction as. 298 func as2variant(as int) int { 299 initvariants() 300 for i := int(0); i < len(varianttable[as]); i++ { 301 if varianttable[as][i] == as { 302 return i 303 } 304 } 305 gc.Fatal("as2variant: instruction %v is not a variant of itself", obj.Aconv(as)) 306 return 0 307 } 308 309 // variant2as returns the instruction as with the given variant (V_*) flags. 310 // If no such variant exists, this returns 0. 311 func variant2as(as int, flags int) int { 312 initvariants() 313 return varianttable[as][flags] 314 } 315
