1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc. 2 @c This is part of the GAS manual. 3 @c For copying conditions, see the file as.texinfo. 4 @page 5 @node SH-Dependent 6 @chapter Renesas / SuperH SH Dependent Features 7 8 @cindex SH support 9 @menu 10 * SH Options:: Options 11 * SH Syntax:: Syntax 12 * SH Floating Point:: Floating Point 13 * SH Directives:: SH Machine Directives 14 * SH Opcodes:: Opcodes 15 @end menu 16 17 @node SH Options 18 @section Options 19 20 @cindex SH options 21 @cindex options, SH 22 @code{@value{AS}} has following command-line options for the Renesas 23 (formerly Hitachi) / SuperH SH family. 24 25 @table @code 26 @kindex --little 27 @kindex --big 28 @kindex --relax 29 @kindex --small 30 @kindex --dsp 31 @kindex --renesas 32 @kindex --allow-reg-prefix 33 34 @item --little 35 Generate little endian code. 36 37 @item --big 38 Generate big endian code. 39 40 @item --relax 41 Alter jump instructions for long displacements. 42 43 @item --small 44 Align sections to 4 byte boundaries, not 16. 45 46 @item --dsp 47 Enable sh-dsp insns, and disable sh3e / sh4 insns. 48 49 @item --renesas 50 Disable optimization with section symbol for compatibility with 51 Renesas assembler. 52 53 @item --allow-reg-prefix 54 Allow '$' as a register name prefix. 55 56 @kindex --fdpic 57 @item --fdpic 58 Generate an FDPIC object file. 59 60 @item --isa=sh4 | sh4a 61 Specify the sh4 or sh4a instruction set. 62 @item --isa=dsp 63 Enable sh-dsp insns, and disable sh3e / sh4 insns. 64 @item --isa=fp 65 Enable sh2e, sh3e, sh4, and sh4a insn sets. 66 @item --isa=all 67 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 68 69 @item -h-tick-hex 70 Support H'00 style hex constants in addition to 0x00 style. 71 72 @end table 73 74 @node SH Syntax 75 @section Syntax 76 77 @menu 78 * SH-Chars:: Special Characters 79 * SH-Regs:: Register Names 80 * SH-Addressing:: Addressing Modes 81 @end menu 82 83 @node SH-Chars 84 @subsection Special Characters 85 86 @cindex line comment character, SH 87 @cindex SH line comment character 88 @samp{!} is the line comment character. 89 90 @cindex line separator, SH 91 @cindex statement separator, SH 92 @cindex SH line separator 93 You can use @samp{;} instead of a newline to separate statements. 94 95 If a @samp{#} appears as the first character of a line then the whole 96 line is treated as a comment, but in this case the line could also be 97 a logical line number directive (@pxref{Comments}) or a preprocessor 98 control command (@pxref{Preprocessing}). 99 100 @cindex symbol names, @samp{$} in 101 @cindex @code{$} in symbol names 102 Since @samp{$} has no special meaning, you may use it in symbol names. 103 104 @node SH-Regs 105 @subsection Register Names 106 107 @cindex SH registers 108 @cindex registers, SH 109 You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2}, 110 @samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8}, 111 @samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14}, 112 and @samp{r15} to refer to the SH registers. 113 114 The SH also has these control registers: 115 116 @table @code 117 @item pr 118 procedure register (holds return address) 119 120 @item pc 121 program counter 122 123 @item mach 124 @itemx macl 125 high and low multiply accumulator registers 126 127 @item sr 128 status register 129 130 @item gbr 131 global base register 132 133 @item vbr 134 vector base register (for interrupt vectors) 135 @end table 136 137 @node SH-Addressing 138 @subsection Addressing Modes 139 140 @cindex addressing modes, SH 141 @cindex SH addressing modes 142 @code{@value{AS}} understands the following addressing modes for the SH. 143 @code{R@var{n}} in the following refers to any of the numbered 144 registers, but @emph{not} the control registers. 145 146 @table @code 147 @item R@var{n} 148 Register direct 149 150 @item @@R@var{n} 151 Register indirect 152 153 @item @@-R@var{n} 154 Register indirect with pre-decrement 155 156 @item @@R@var{n}+ 157 Register indirect with post-increment 158 159 @item @@(@var{disp}, R@var{n}) 160 Register indirect with displacement 161 162 @item @@(R0, R@var{n}) 163 Register indexed 164 165 @item @@(@var{disp}, GBR) 166 @code{GBR} offset 167 168 @item @@(R0, GBR) 169 GBR indexed 170 171 @item @var{addr} 172 @itemx @@(@var{disp}, PC) 173 PC relative address (for branch or for addressing memory). The 174 @code{@value{AS}} implementation allows you to use the simpler form 175 @var{addr} anywhere a PC relative address is called for; the alternate 176 form is supported for compatibility with other assemblers. 177 178 @item #@var{imm} 179 Immediate data 180 @end table 181 182 @node SH Floating Point 183 @section Floating Point 184 185 @cindex floating point, SH (@sc{ieee}) 186 @cindex SH floating point (@sc{ieee}) 187 SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 188 SH groups can use @code{.float} directive to generate @sc{ieee} 189 floating-point numbers. 190 191 SH2E and SH3E support single-precision floating point calculations as 192 well as entirely PCAPI compatible emulation of double-precision 193 floating point calculations. SH2E and SH3E instructions are a subset of 194 the floating point calculations conforming to the IEEE754 standard. 195 196 In addition to single-precision and double-precision floating-point 197 operation capability, the on-chip FPU of SH4 has a 128-bit graphic 198 engine that enables 32-bit floating-point data to be processed 128 199 bits at a time. It also supports 4 * 4 array operations and inner 200 product operations. Also, a superscalar architecture is employed that 201 enables simultaneous execution of two instructions (including FPU 202 instructions), providing performance of up to twice that of 203 conventional architectures at the same frequency. 204 205 @node SH Directives 206 @section SH Machine Directives 207 208 @cindex SH machine directives 209 @cindex machine directives, SH 210 @cindex @code{uaword} directive, SH 211 @cindex @code{ualong} directive, SH 212 @cindex @code{uaquad} directive, SH 213 214 @table @code 215 @item uaword 216 @itemx ualong 217 @itemx uaquad 218 @code{@value{AS}} will issue a warning when a misaligned @code{.word}, 219 @code{.long}, or @code{.quad} directive is used. You may use 220 @code{.uaword}, @code{.ualong}, or @code{.uaquad} to indicate that the 221 value is intentionally misaligned. 222 @end table 223 224 @node SH Opcodes 225 @section Opcodes 226 227 @cindex SH opcode summary 228 @cindex opcode summary, SH 229 @cindex mnemonics, SH 230 @cindex instruction summary, SH 231 For detailed information on the SH machine instruction set, see 232 @cite{SH-Microcomputer User's Manual} (Renesas) or 233 @cite{SH-4 32-bit CPU Core Architecture} (SuperH) and 234 @cite{SuperH (SH) 64-Bit RISC Series} (SuperH). 235 236 @code{@value{AS}} implements all the standard SH opcodes. No additional 237 pseudo-instructions are needed on this family. Note, however, that 238 because @code{@value{AS}} supports a simpler form of PC-relative 239 addressing, you may simply write (for example) 240 241 @example 242 mov.l bar,r0 243 @end example 244 245 @noindent 246 where other assemblers might require an explicit displacement to 247 @code{bar} from the program counter: 248 249 @example 250 mov.l @@(@var{disp}, PC) 251 @end example 252 253 @ifset SMALL 254 @c this table, due to the multi-col faking and hardcoded order, looks silly 255 @c except in smallbook. See comments below "@set SMALL" near top of this file. 256 257 Here is a summary of SH opcodes: 258 259 @page 260 @smallexample 261 @i{Legend:} 262 Rn @r{a numbered register} 263 Rm @r{another numbered register} 264 #imm @r{immediate data} 265 disp @r{displacement} 266 disp8 @r{8-bit displacement} 267 disp12 @r{12-bit displacement} 268 269 add #imm,Rn lds.l @@Rn+,PR 270 add Rm,Rn mac.w @@Rm+,@@Rn+ 271 addc Rm,Rn mov #imm,Rn 272 addv Rm,Rn mov Rm,Rn 273 and #imm,R0 mov.b Rm,@@(R0,Rn) 274 and Rm,Rn mov.b Rm,@@-Rn 275 and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn 276 bf disp8 mov.b @@(disp,Rm),R0 277 bra disp12 mov.b @@(disp,GBR),R0 278 bsr disp12 mov.b @@(R0,Rm),Rn 279 bt disp8 mov.b @@Rm+,Rn 280 clrmac mov.b @@Rm,Rn 281 clrt mov.b R0,@@(disp,Rm) 282 cmp/eq #imm,R0 mov.b R0,@@(disp,GBR) 283 cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn) 284 cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn) 285 cmp/gt Rm,Rn mov.l Rm,@@-Rn 286 cmp/hi Rm,Rn mov.l Rm,@@Rn 287 cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm 288 cmp/pl Rn mov.l @@(disp,GBR),R0 289 cmp/pz Rn mov.l @@(disp,PC),Rn 290 cmp/str Rm,Rn mov.l @@(R0,Rm),Rn 291 div0s Rm,Rn mov.l @@Rm+,Rn 292 div0u mov.l @@Rm,Rn 293 div1 Rm,Rn mov.l R0,@@(disp,GBR) 294 exts.b Rm,Rn mov.w Rm,@@(R0,Rn) 295 exts.w Rm,Rn mov.w Rm,@@-Rn 296 extu.b Rm,Rn mov.w Rm,@@Rn 297 extu.w Rm,Rn mov.w @@(disp,Rm),R0 298 jmp @@Rn mov.w @@(disp,GBR),R0 299 jsr @@Rn mov.w @@(disp,PC),Rn 300 ldc Rn,GBR mov.w @@(R0,Rm),Rn 301 ldc Rn,SR mov.w @@Rm+,Rn 302 ldc Rn,VBR mov.w @@Rm,Rn 303 ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm) 304 ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR) 305 ldc.l @@Rn+,VBR mova @@(disp,PC),R0 306 lds Rn,MACH movt Rn 307 lds Rn,MACL muls Rm,Rn 308 lds Rn,PR mulu Rm,Rn 309 lds.l @@Rn+,MACH neg Rm,Rn 310 lds.l @@Rn+,MACL negc Rm,Rn 311 @page 312 nop stc VBR,Rn 313 not Rm,Rn stc.l GBR,@@-Rn 314 or #imm,R0 stc.l SR,@@-Rn 315 or Rm,Rn stc.l VBR,@@-Rn 316 or.b #imm,@@(R0,GBR) sts MACH,Rn 317 rotcl Rn sts MACL,Rn 318 rotcr Rn sts PR,Rn 319 rotl Rn sts.l MACH,@@-Rn 320 rotr Rn sts.l MACL,@@-Rn 321 rte sts.l PR,@@-Rn 322 rts sub Rm,Rn 323 sett subc Rm,Rn 324 shal Rn subv Rm,Rn 325 shar Rn swap.b Rm,Rn 326 shll Rn swap.w Rm,Rn 327 shll16 Rn tas.b @@Rn 328 shll2 Rn trapa #imm 329 shll8 Rn tst #imm,R0 330 shlr Rn tst Rm,Rn 331 shlr16 Rn tst.b #imm,@@(R0,GBR) 332 shlr2 Rn xor #imm,R0 333 shlr8 Rn xor Rm,Rn 334 sleep xor.b #imm,@@(R0,GBR) 335 stc GBR,Rn xtrct Rm,Rn 336 stc SR,Rn 337 @end smallexample 338 @end ifset 339 340 @ifset Renesas-all 341 @ifclear GENERIC 342 @raisesections 343 @end ifclear 344 @end ifset 345 346
