Lines Matching refs:Mips
16 #include "Mips.h"
37 #define DEBUG_TYPE "mips-isel"
53 MIB.addReg(Mips::DSPPos, Flag);
56 MIB.addReg(Mips::DSPSCount, Flag);
59 MIB.addReg(Mips::DSPCarry, Flag);
62 MIB.addReg(Mips::DSPOutFlag, Flag);
65 MIB.addReg(Mips::DSPCCond, Flag);
68 MIB.addReg(Mips::DSPEFI, Flag);
75 case 0: return Mips::MSAIR;
76 case 1: return Mips::MSACSR;
77 case 2: return Mips::MSAAccess;
78 case 3: return Mips::MSASave;
79 case 4: return Mips::MSAModify;
80 case 5: return Mips::MSARequest;
81 case 6: return Mips::MSAMap;
82 case 7: return Mips::MSAUnmap;
91 if ((MI.getOpcode() == Mips::ADDiu) &&
92 (MI.getOperand(1).getReg() == Mips::ZERO) &&
95 ZeroReg = Mips::ZERO;
96 } else if ((MI.getOpcode() == Mips::DADDiu) &&
97 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
100 ZeroReg = Mips::ZERO_64;
143 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
149 MF.getRegInfo().addLiveIn(Mips::T9_64);
150 MBB.addLiveIn(Mips::T9_64);
156 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
158 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
159 .addReg(Mips::T9_64);
160 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
170 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
172 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
177 MF.getRegInfo().addLiveIn(Mips::T9);
178 MBB.addLiveIn(Mips::T9);
185 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
187 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
188 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
209 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
212 MF.getRegInfo().addLiveIn(Mips::V0);
213 MBB.addLiveIn(Mips::V0);
214 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
215 .addReg(Mips::V0).addReg(Mips::T9);
226 if (I->getOpcode() == Mips::RDDSP)
228 else if (I->getOpcode() == Mips::WRDSP)
244 unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
246 SLTuOp = Mips::SLTu64;
247 ADDuOp = Mips::DADDu;
260 Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
263 CurDAG->getTargetConstant(Mips::sub_32, DL,
316 /// Used on Mips Load/Store instructions
366 /// Used on Mips Load/Store instructions
720 unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
729 unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
739 Mips::ZERO_64, MVT::i64);
740 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
743 Mips::ZERO, MVT::i32);
744 Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
748 Mips::ZERO, MVT::i32);
749 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
780 if (Inst->Opc == Mips::LUi64)
785 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
824 CurDAG->getMachineNode(Mips::MOVE_V, DL,
853 RdhwrOpc = Mips::RDHWR;
854 DestReg = Mips::V1;
856 RdhwrOpc = Mips::RDHWR64;
857 DestReg = Mips::V1_64;
863 CurDAG->getRegister(Mips::HWR29, MVT::i32));
904 LdiOp = Mips::LDI_B;
908 LdiOp = Mips::LDI_H;
912 LdiOp = Mips::LDI_W;
916 LdiOp = Mips::LDI_D;
937 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
