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      1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "MipsSEISelDAGToDAG.h"
     15 #include "MCTargetDesc/MipsBaseInfo.h"
     16 #include "Mips.h"
     17 #include "MipsAnalyzeImmediate.h"
     18 #include "MipsMachineFunction.h"
     19 #include "MipsRegisterInfo.h"
     20 #include "llvm/CodeGen/MachineConstantPool.h"
     21 #include "llvm/CodeGen/MachineFrameInfo.h"
     22 #include "llvm/CodeGen/MachineFunction.h"
     23 #include "llvm/CodeGen/MachineInstrBuilder.h"
     24 #include "llvm/CodeGen/MachineRegisterInfo.h"
     25 #include "llvm/CodeGen/SelectionDAGNodes.h"
     26 #include "llvm/IR/CFG.h"
     27 #include "llvm/IR/GlobalValue.h"
     28 #include "llvm/IR/Instructions.h"
     29 #include "llvm/IR/Intrinsics.h"
     30 #include "llvm/IR/Type.h"
     31 #include "llvm/Support/Debug.h"
     32 #include "llvm/Support/ErrorHandling.h"
     33 #include "llvm/Support/raw_ostream.h"
     34 #include "llvm/Target/TargetMachine.h"
     35 using namespace llvm;
     36 
     37 #define DEBUG_TYPE "mips-isel"
     38 
     39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
     40   Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
     41   if (Subtarget->inMips16Mode())
     42     return false;
     43   return MipsDAGToDAGISel::runOnMachineFunction(MF);
     44 }
     45 
     46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
     47                                                MachineFunction &MF) {
     48   MachineInstrBuilder MIB(MF, &MI);
     49   unsigned Mask = MI.getOperand(1).getImm();
     50   unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
     51 
     52   if (Mask & 1)
     53     MIB.addReg(Mips::DSPPos, Flag);
     54 
     55   if (Mask & 2)
     56     MIB.addReg(Mips::DSPSCount, Flag);
     57 
     58   if (Mask & 4)
     59     MIB.addReg(Mips::DSPCarry, Flag);
     60 
     61   if (Mask & 8)
     62     MIB.addReg(Mips::DSPOutFlag, Flag);
     63 
     64   if (Mask & 16)
     65     MIB.addReg(Mips::DSPCCond, Flag);
     66 
     67   if (Mask & 32)
     68     MIB.addReg(Mips::DSPEFI, Flag);
     69 }
     70 
     71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
     72   switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
     73   default:
     74     llvm_unreachable("Could not map int to register");
     75   case 0: return Mips::MSAIR;
     76   case 1: return Mips::MSACSR;
     77   case 2: return Mips::MSAAccess;
     78   case 3: return Mips::MSASave;
     79   case 4: return Mips::MSAModify;
     80   case 5: return Mips::MSARequest;
     81   case 6: return Mips::MSAMap;
     82   case 7: return Mips::MSAUnmap;
     83   }
     84 }
     85 
     86 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
     87                                                 const MachineInstr& MI) {
     88   unsigned DstReg = 0, ZeroReg = 0;
     89 
     90   // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
     91   if ((MI.getOpcode() == Mips::ADDiu) &&
     92       (MI.getOperand(1).getReg() == Mips::ZERO) &&
     93       (MI.getOperand(2).getImm() == 0)) {
     94     DstReg = MI.getOperand(0).getReg();
     95     ZeroReg = Mips::ZERO;
     96   } else if ((MI.getOpcode() == Mips::DADDiu) &&
     97              (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
     98              (MI.getOperand(2).getImm() == 0)) {
     99     DstReg = MI.getOperand(0).getReg();
    100     ZeroReg = Mips::ZERO_64;
    101   }
    102 
    103   if (!DstReg)
    104     return false;
    105 
    106   // Replace uses with ZeroReg.
    107   for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
    108        E = MRI->use_end(); U != E;) {
    109     MachineOperand &MO = *U;
    110     unsigned OpNo = U.getOperandNo();
    111     MachineInstr *MI = MO.getParent();
    112     ++U;
    113 
    114     // Do not replace if it is a phi's operand or is tied to def operand.
    115     if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
    116       continue;
    117 
    118     // Also, we have to check that the register class of the operand
    119     // contains the zero register.
    120     if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
    121       continue;
    122 
    123     MO.setReg(ZeroReg);
    124   }
    125 
    126   return true;
    127 }
    128 
    129 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
    130   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
    131 
    132   if (!MipsFI->globalBaseRegSet())
    133     return;
    134 
    135   MachineBasicBlock &MBB = MF.front();
    136   MachineBasicBlock::iterator I = MBB.begin();
    137   MachineRegisterInfo &RegInfo = MF.getRegInfo();
    138   const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
    139   DebugLoc DL;
    140   unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
    141   const TargetRegisterClass *RC;
    142   const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
    143   RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
    144 
    145   V0 = RegInfo.createVirtualRegister(RC);
    146   V1 = RegInfo.createVirtualRegister(RC);
    147 
    148   if (ABI.IsN64()) {
    149     MF.getRegInfo().addLiveIn(Mips::T9_64);
    150     MBB.addLiveIn(Mips::T9_64);
    151 
    152     // lui $v0, %hi(%neg(%gp_rel(fname)))
    153     // daddu $v1, $v0, $t9
    154     // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
    155     const GlobalValue *FName = MF.getFunction();
    156     BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
    157       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
    158     BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
    159       .addReg(Mips::T9_64);
    160     BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
    161       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
    162     return;
    163   }
    164 
    165   if (MF.getTarget().getRelocationModel() == Reloc::Static) {
    166     // Set global register to __gnu_local_gp.
    167     //
    168     // lui   $v0, %hi(__gnu_local_gp)
    169     // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
    170     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
    171       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
    172     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
    173       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
    174     return;
    175   }
    176 
    177   MF.getRegInfo().addLiveIn(Mips::T9);
    178   MBB.addLiveIn(Mips::T9);
    179 
    180   if (ABI.IsN32()) {
    181     // lui $v0, %hi(%neg(%gp_rel(fname)))
    182     // addu $v1, $v0, $t9
    183     // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
    184     const GlobalValue *FName = MF.getFunction();
    185     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
    186       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
    187     BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
    188     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
    189       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
    190     return;
    191   }
    192 
    193   assert(ABI.IsO32());
    194 
    195   // For O32 ABI, the following instruction sequence is emitted to initialize
    196   // the global base register:
    197   //
    198   //  0. lui   $2, %hi(_gp_disp)
    199   //  1. addiu $2, $2, %lo(_gp_disp)
    200   //  2. addu  $globalbasereg, $2, $t9
    201   //
    202   // We emit only the last instruction here.
    203   //
    204   // GNU linker requires that the first two instructions appear at the beginning
    205   // of a function and no instructions be inserted before or between them.
    206   // The two instructions are emitted during lowering to MC layer in order to
    207   // avoid any reordering.
    208   //
    209   // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
    210   // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
    211   // reads it.
    212   MF.getRegInfo().addLiveIn(Mips::V0);
    213   MBB.addLiveIn(Mips::V0);
    214   BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
    215     .addReg(Mips::V0).addReg(Mips::T9);
    216 }
    217 
    218 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
    219   initGlobalBaseReg(MF);
    220 
    221   MachineRegisterInfo *MRI = &MF.getRegInfo();
    222 
    223   for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
    224        ++MFI)
    225     for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
    226       if (I->getOpcode() == Mips::RDDSP)
    227         addDSPCtrlRegOperands(false, *I, MF);
    228       else if (I->getOpcode() == Mips::WRDSP)
    229         addDSPCtrlRegOperands(true, *I, MF);
    230       else
    231         replaceUsesWithZeroReg(MRI, *I);
    232     }
    233 }
    234 
    235 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
    236                                            SDValue CmpLHS, SDLoc DL,
    237                                            SDNode *Node) const {
    238   unsigned Opc = InFlag.getOpcode(); (void)Opc;
    239 
    240   assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
    241           (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
    242          "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
    243 
    244   unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
    245   if (Subtarget->isGP64bit()) {
    246     SLTuOp = Mips::SLTu64;
    247     ADDuOp = Mips::DADDu;
    248   }
    249 
    250   SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
    251   SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
    252   EVT VT = LHS.getValueType();
    253 
    254   SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);
    255 
    256   if (Subtarget->isGP64bit()) {
    257     // On 64-bit targets, sltu produces an i64 but our backend currently says
    258     // that SLTu64 produces an i32. We need to fix this in the long run but for
    259     // now, just make the DAG type-correct by asserting the upper bits are zero.
    260     Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
    261                                    CurDAG->getTargetConstant(0, DL, VT),
    262                                    SDValue(Carry, 0),
    263                                    CurDAG->getTargetConstant(Mips::sub_32, DL,
    264                                                              VT));
    265   }
    266 
    267   // Generate a second addition only if we know that RHS is not a
    268   // constant-zero node.
    269   SDNode *AddCarry = Carry;
    270   ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
    271   if (!C || C->getZExtValue())
    272     AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS);
    273 
    274   return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
    275                               SDValue(AddCarry, 0));
    276 }
    277 
    278 /// Match frameindex
    279 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
    280                                               SDValue &Offset) const {
    281   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
    282     EVT ValTy = Addr.getValueType();
    283 
    284     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
    285     Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
    286     return true;
    287   }
    288   return false;
    289 }
    290 
    291 /// Match frameindex+offset and frameindex|offset
    292 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
    293                                                     SDValue &Offset,
    294                                                     unsigned OffsetBits) const {
    295   if (CurDAG->isBaseWithConstantOffset(Addr)) {
    296     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
    297     if (isIntN(OffsetBits, CN->getSExtValue())) {
    298       EVT ValTy = Addr.getValueType();
    299 
    300       // If the first operand is a FI, get the TargetFI Node
    301       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
    302                                   (Addr.getOperand(0)))
    303         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
    304       else
    305         Base = Addr.getOperand(0);
    306 
    307       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
    308                                          ValTy);
    309       return true;
    310     }
    311   }
    312   return false;
    313 }
    314 
    315 /// ComplexPattern used on MipsInstrInfo
    316 /// Used on Mips Load/Store instructions
    317 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
    318                                           SDValue &Offset) const {
    319   // if Address is FI, get the TargetFrameIndex.
    320   if (selectAddrFrameIndex(Addr, Base, Offset))
    321     return true;
    322 
    323   // on PIC code Load GA
    324   if (Addr.getOpcode() == MipsISD::Wrapper) {
    325     Base   = Addr.getOperand(0);
    326     Offset = Addr.getOperand(1);
    327     return true;
    328   }
    329 
    330   if (TM.getRelocationModel() != Reloc::PIC_) {
    331     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
    332         Addr.getOpcode() == ISD::TargetGlobalAddress))
    333       return false;
    334   }
    335 
    336   // Addresses of the form FI+const or FI|const
    337   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
    338     return true;
    339 
    340   // Operand is a result from an ADD.
    341   if (Addr.getOpcode() == ISD::ADD) {
    342     // When loading from constant pools, load the lower address part in
    343     // the instruction itself. Example, instead of:
    344     //  lui $2, %hi($CPI1_0)
    345     //  addiu $2, $2, %lo($CPI1_0)
    346     //  lwc1 $f0, 0($2)
    347     // Generate:
    348     //  lui $2, %hi($CPI1_0)
    349     //  lwc1 $f0, %lo($CPI1_0)($2)
    350     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
    351         Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
    352       SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
    353       if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
    354           isa<JumpTableSDNode>(Opnd0)) {
    355         Base = Addr.getOperand(0);
    356         Offset = Opnd0;
    357         return true;
    358       }
    359     }
    360   }
    361 
    362   return false;
    363 }
    364 
    365 /// ComplexPattern used on MipsInstrInfo
    366 /// Used on Mips Load/Store instructions
    367 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
    368                                           SDValue &Offset) const {
    369   // Operand is a result from an ADD.
    370   if (Addr.getOpcode() == ISD::ADD) {
    371     Base = Addr.getOperand(0);
    372     Offset = Addr.getOperand(1);
    373     return true;
    374   }
    375 
    376   return false;
    377 }
    378 
    379 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
    380                                            SDValue &Offset) const {
    381   Base = Addr;
    382   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
    383   return true;
    384 }
    385 
    386 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
    387                                        SDValue &Offset) const {
    388   return selectAddrRegImm(Addr, Base, Offset) ||
    389     selectAddrDefault(Addr, Base, Offset);
    390 }
    391 
    392 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
    393                                            SDValue &Offset) const {
    394   if (selectAddrFrameIndex(Addr, Base, Offset))
    395     return true;
    396 
    397   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
    398     return true;
    399 
    400   return false;
    401 }
    402 
    403 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
    404                                             SDValue &Offset) const {
    405   if (selectAddrFrameIndex(Addr, Base, Offset))
    406     return true;
    407 
    408   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
    409     return true;
    410 
    411   return false;
    412 }
    413 
    414 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
    415 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
    416                                             SDValue &Offset) const {
    417   if (selectAddrFrameIndex(Addr, Base, Offset))
    418     return true;
    419 
    420   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
    421     return true;
    422 
    423   return false;
    424 }
    425 
    426 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
    427                                             SDValue &Offset) const {
    428   if (selectAddrFrameIndex(Addr, Base, Offset))
    429     return true;
    430 
    431   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
    432     return true;
    433 
    434   return false;
    435 }
    436 
    437 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
    438                                          SDValue &Offset) const {
    439   return selectAddrRegImm12(Addr, Base, Offset) ||
    440     selectAddrDefault(Addr, Base, Offset);
    441 }
    442 
    443 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
    444                                              SDValue &Offset) const {
    445   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
    446     if (isa<FrameIndexSDNode>(Base))
    447       return false;
    448 
    449     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
    450       unsigned CnstOff = CN->getZExtValue();
    451       return (CnstOff == (CnstOff & 0x3c));
    452     }
    453 
    454     return false;
    455   }
    456 
    457   // For all other cases where "lw" would be selected, don't select "lw16"
    458   // because it would result in additional instructions to prepare operands.
    459   if (selectAddrRegImm(Addr, Base, Offset))
    460     return false;
    461 
    462   return selectAddrDefault(Addr, Base, Offset);
    463 }
    464 
    465 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
    466                                           SDValue &Offset) const {
    467   if (selectAddrRegImm10(Addr, Base, Offset))
    468     return true;
    469 
    470   if (selectAddrDefault(Addr, Base, Offset))
    471     return true;
    472 
    473   return false;
    474 }
    475 
    476 // Select constant vector splats.
    477 //
    478 // Returns true and sets Imm if:
    479 // * MSA is enabled
    480 // * N is a ISD::BUILD_VECTOR representing a constant splat
    481 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
    482                                       unsigned MinSizeInBits) const {
    483   if (!Subtarget->hasMSA())
    484     return false;
    485 
    486   BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
    487 
    488   if (!Node)
    489     return false;
    490 
    491   APInt SplatValue, SplatUndef;
    492   unsigned SplatBitSize;
    493   bool HasAnyUndefs;
    494 
    495   if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
    496                              MinSizeInBits, !Subtarget->isLittle()))
    497     return false;
    498 
    499   Imm = SplatValue;
    500 
    501   return true;
    502 }
    503 
    504 // Select constant vector splats.
    505 //
    506 // In addition to the requirements of selectVSplat(), this function returns
    507 // true and sets Imm if:
    508 // * The splat value is the same width as the elements of the vector
    509 // * The splat value fits in an integer with the specified signed-ness and
    510 //   width.
    511 //
    512 // This function looks through ISD::BITCAST nodes.
    513 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    514 //       sometimes a shuffle in big-endian mode.
    515 //
    516 // It's worth noting that this function is not used as part of the selection
    517 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
    518 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
    519 // MipsSEDAGToDAGISel::selectNode.
    520 bool MipsSEDAGToDAGISel::
    521 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
    522                    unsigned ImmBitSize) const {
    523   APInt ImmValue;
    524   EVT EltTy = N->getValueType(0).getVectorElementType();
    525 
    526   if (N->getOpcode() == ISD::BITCAST)
    527     N = N->getOperand(0);
    528 
    529   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
    530       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    531 
    532     if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
    533         (!Signed && ImmValue.isIntN(ImmBitSize))) {
    534       Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
    535       return true;
    536     }
    537   }
    538 
    539   return false;
    540 }
    541 
    542 // Select constant vector splats.
    543 bool MipsSEDAGToDAGISel::
    544 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
    545   return selectVSplatCommon(N, Imm, false, 1);
    546 }
    547 
    548 bool MipsSEDAGToDAGISel::
    549 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
    550   return selectVSplatCommon(N, Imm, false, 2);
    551 }
    552 
    553 bool MipsSEDAGToDAGISel::
    554 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
    555   return selectVSplatCommon(N, Imm, false, 3);
    556 }
    557 
    558 // Select constant vector splats.
    559 bool MipsSEDAGToDAGISel::
    560 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
    561   return selectVSplatCommon(N, Imm, false, 4);
    562 }
    563 
    564 // Select constant vector splats.
    565 bool MipsSEDAGToDAGISel::
    566 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
    567   return selectVSplatCommon(N, Imm, false, 5);
    568 }
    569 
    570 // Select constant vector splats.
    571 bool MipsSEDAGToDAGISel::
    572 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
    573   return selectVSplatCommon(N, Imm, false, 6);
    574 }
    575 
    576 // Select constant vector splats.
    577 bool MipsSEDAGToDAGISel::
    578 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
    579   return selectVSplatCommon(N, Imm, false, 8);
    580 }
    581 
    582 // Select constant vector splats.
    583 bool MipsSEDAGToDAGISel::
    584 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
    585   return selectVSplatCommon(N, Imm, true, 5);
    586 }
    587 
    588 // Select constant vector splats whose value is a power of 2.
    589 //
    590 // In addition to the requirements of selectVSplat(), this function returns
    591 // true and sets Imm if:
    592 // * The splat value is the same width as the elements of the vector
    593 // * The splat value is a power of two.
    594 //
    595 // This function looks through ISD::BITCAST nodes.
    596 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    597 //       sometimes a shuffle in big-endian mode.
    598 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
    599   APInt ImmValue;
    600   EVT EltTy = N->getValueType(0).getVectorElementType();
    601 
    602   if (N->getOpcode() == ISD::BITCAST)
    603     N = N->getOperand(0);
    604 
    605   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
    606       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    607     int32_t Log2 = ImmValue.exactLogBase2();
    608 
    609     if (Log2 != -1) {
    610       Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
    611       return true;
    612     }
    613   }
    614 
    615   return false;
    616 }
    617 
    618 // Select constant vector splats whose value only has a consecutive sequence
    619 // of left-most bits set (e.g. 0b11...1100...00).
    620 //
    621 // In addition to the requirements of selectVSplat(), this function returns
    622 // true and sets Imm if:
    623 // * The splat value is the same width as the elements of the vector
    624 // * The splat value is a consecutive sequence of left-most bits.
    625 //
    626 // This function looks through ISD::BITCAST nodes.
    627 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    628 //       sometimes a shuffle in big-endian mode.
    629 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
    630   APInt ImmValue;
    631   EVT EltTy = N->getValueType(0).getVectorElementType();
    632 
    633   if (N->getOpcode() == ISD::BITCAST)
    634     N = N->getOperand(0);
    635 
    636   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
    637       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    638     // Extract the run of set bits starting with bit zero from the bitwise
    639     // inverse of ImmValue, and test that the inverse of this is the same
    640     // as the original value.
    641     if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
    642 
    643       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), SDLoc(N),
    644                                       EltTy);
    645       return true;
    646     }
    647   }
    648 
    649   return false;
    650 }
    651 
    652 // Select constant vector splats whose value only has a consecutive sequence
    653 // of right-most bits set (e.g. 0b00...0011...11).
    654 //
    655 // In addition to the requirements of selectVSplat(), this function returns
    656 // true and sets Imm if:
    657 // * The splat value is the same width as the elements of the vector
    658 // * The splat value is a consecutive sequence of right-most bits.
    659 //
    660 // This function looks through ISD::BITCAST nodes.
    661 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    662 //       sometimes a shuffle in big-endian mode.
    663 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
    664   APInt ImmValue;
    665   EVT EltTy = N->getValueType(0).getVectorElementType();
    666 
    667   if (N->getOpcode() == ISD::BITCAST)
    668     N = N->getOperand(0);
    669 
    670   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
    671       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    672     // Extract the run of set bits starting with bit zero, and test that the
    673     // result is the same as the original value
    674     if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
    675       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), SDLoc(N),
    676                                       EltTy);
    677       return true;
    678     }
    679   }
    680 
    681   return false;
    682 }
    683 
    684 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
    685                                                  SDValue &Imm) const {
    686   APInt ImmValue;
    687   EVT EltTy = N->getValueType(0).getVectorElementType();
    688 
    689   if (N->getOpcode() == ISD::BITCAST)
    690     N = N->getOperand(0);
    691 
    692   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
    693       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    694     int32_t Log2 = (~ImmValue).exactLogBase2();
    695 
    696     if (Log2 != -1) {
    697       Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
    698       return true;
    699     }
    700   }
    701 
    702   return false;
    703 }
    704 
    705 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
    706   unsigned Opcode = Node->getOpcode();
    707   SDLoc DL(Node);
    708 
    709   ///
    710   // Instruction Selection not handled by the auto-generated
    711   // tablegen selection should be handled here.
    712   ///
    713   SDNode *Result;
    714 
    715   switch(Opcode) {
    716   default: break;
    717 
    718   case ISD::SUBE: {
    719     SDValue InFlag = Node->getOperand(2);
    720     unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
    721     Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);
    722     return std::make_pair(true, Result);
    723   }
    724 
    725   case ISD::ADDE: {
    726     if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
    727       break;
    728     SDValue InFlag = Node->getOperand(2);
    729     unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
    730     Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
    731     return std::make_pair(true, Result);
    732   }
    733 
    734   case ISD::ConstantFP: {
    735     ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
    736     if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
    737       if (Subtarget->isGP64bit()) {
    738         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
    739                                               Mips::ZERO_64, MVT::i64);
    740         Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
    741       } else if (Subtarget->isFP64bit()) {
    742         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
    743                                               Mips::ZERO, MVT::i32);
    744         Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
    745                                         Zero, Zero);
    746       } else {
    747         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
    748                                               Mips::ZERO, MVT::i32);
    749         Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
    750                                         Zero);
    751       }
    752 
    753       return std::make_pair(true, Result);
    754     }
    755     break;
    756   }
    757 
    758   case ISD::Constant: {
    759     const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
    760     unsigned Size = CN->getValueSizeInBits(0);
    761 
    762     if (Size == 32)
    763       break;
    764 
    765     MipsAnalyzeImmediate AnalyzeImm;
    766     int64_t Imm = CN->getSExtValue();
    767 
    768     const MipsAnalyzeImmediate::InstSeq &Seq =
    769       AnalyzeImm.Analyze(Imm, Size, false);
    770 
    771     MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
    772     SDLoc DL(CN);
    773     SDNode *RegOpnd;
    774     SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
    775                                                 DL, MVT::i64);
    776 
    777     // The first instruction can be a LUi which is different from other
    778     // instructions (ADDiu, ORI and SLL) in that it does not have a register
    779     // operand.
    780     if (Inst->Opc == Mips::LUi64)
    781       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
    782     else
    783       RegOpnd =
    784         CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
    785                                CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
    786                                ImmOpnd);
    787 
    788     // The remaining instructions in the sequence are handled here.
    789     for (++Inst; Inst != Seq.end(); ++Inst) {
    790       ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
    791                                           MVT::i64);
    792       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
    793                                        SDValue(RegOpnd, 0), ImmOpnd);
    794     }
    795 
    796     return std::make_pair(true, RegOpnd);
    797   }
    798 
    799   case ISD::INTRINSIC_W_CHAIN: {
    800     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
    801     default:
    802       break;
    803 
    804     case Intrinsic::mips_cfcmsa: {
    805       SDValue ChainIn = Node->getOperand(0);
    806       SDValue RegIdx = Node->getOperand(2);
    807       SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
    808                                            getMSACtrlReg(RegIdx), MVT::i32);
    809       return std::make_pair(true, Reg.getNode());
    810     }
    811     }
    812     break;
    813   }
    814 
    815   case ISD::INTRINSIC_WO_CHAIN: {
    816     switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
    817     default:
    818       break;
    819 
    820     case Intrinsic::mips_move_v:
    821       // Like an assignment but will always produce a move.v even if
    822       // unnecessary.
    823       return std::make_pair(true,
    824                             CurDAG->getMachineNode(Mips::MOVE_V, DL,
    825                                                    Node->getValueType(0),
    826                                                    Node->getOperand(1)));
    827     }
    828     break;
    829   }
    830 
    831   case ISD::INTRINSIC_VOID: {
    832     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
    833     default:
    834       break;
    835 
    836     case Intrinsic::mips_ctcmsa: {
    837       SDValue ChainIn = Node->getOperand(0);
    838       SDValue RegIdx  = Node->getOperand(2);
    839       SDValue Value   = Node->getOperand(3);
    840       SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
    841                                               getMSACtrlReg(RegIdx), Value);
    842       return std::make_pair(true, ChainOut.getNode());
    843     }
    844     }
    845     break;
    846   }
    847 
    848   case MipsISD::ThreadPointer: {
    849     EVT PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
    850     unsigned RdhwrOpc, DestReg;
    851 
    852     if (PtrVT == MVT::i32) {
    853       RdhwrOpc = Mips::RDHWR;
    854       DestReg = Mips::V1;
    855     } else {
    856       RdhwrOpc = Mips::RDHWR64;
    857       DestReg = Mips::V1_64;
    858     }
    859 
    860     SDNode *Rdhwr =
    861       CurDAG->getMachineNode(RdhwrOpc, DL,
    862                              Node->getValueType(0),
    863                              CurDAG->getRegister(Mips::HWR29, MVT::i32));
    864     SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
    865                                          SDValue(Rdhwr, 0));
    866     SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
    867     ReplaceUses(SDValue(Node, 0), ResNode);
    868     return std::make_pair(true, ResNode.getNode());
    869   }
    870 
    871   case ISD::BUILD_VECTOR: {
    872     // Select appropriate ldi.[bhwd] instructions for constant splats of
    873     // 128-bit when MSA is enabled. Fixup any register class mismatches that
    874     // occur as a result.
    875     //
    876     // This allows the compiler to use a wider range of immediates than would
    877     // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
    878     // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
    879     // 0x01010101 } without using a constant pool. This would be sub-optimal
    880     // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
    881     // same set/ of registers. Similarly, ldi.h isn't capable of producing {
    882     // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
    883 
    884     BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
    885     APInt SplatValue, SplatUndef;
    886     unsigned SplatBitSize;
    887     bool HasAnyUndefs;
    888     unsigned LdiOp;
    889     EVT ResVecTy = BVN->getValueType(0);
    890     EVT ViaVecTy;
    891 
    892     if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
    893       return std::make_pair(false, nullptr);
    894 
    895     if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
    896                               HasAnyUndefs, 8,
    897                               !Subtarget->isLittle()))
    898       return std::make_pair(false, nullptr);
    899 
    900     switch (SplatBitSize) {
    901     default:
    902       return std::make_pair(false, nullptr);
    903     case 8:
    904       LdiOp = Mips::LDI_B;
    905       ViaVecTy = MVT::v16i8;
    906       break;
    907     case 16:
    908       LdiOp = Mips::LDI_H;
    909       ViaVecTy = MVT::v8i16;
    910       break;
    911     case 32:
    912       LdiOp = Mips::LDI_W;
    913       ViaVecTy = MVT::v4i32;
    914       break;
    915     case 64:
    916       LdiOp = Mips::LDI_D;
    917       ViaVecTy = MVT::v2i64;
    918       break;
    919     }
    920 
    921     if (!SplatValue.isSignedIntN(10))
    922       return std::make_pair(false, nullptr);
    923 
    924     SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
    925                                             ViaVecTy.getVectorElementType());
    926 
    927     SDNode *Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
    928 
    929     if (ResVecTy != ViaVecTy) {
    930       // If LdiOp is writing to a different register class to ResVecTy, then
    931       // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
    932       // since the source and destination register sets contain the same
    933       // registers.
    934       const TargetLowering *TLI = getTargetLowering();
    935       MVT ResVecTySimple = ResVecTy.getSimpleVT();
    936       const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
    937       Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
    938                                    ResVecTy, SDValue(Res, 0),
    939                                    CurDAG->getTargetConstant(RC->getID(), DL,
    940                                                              MVT::i32));
    941     }
    942 
    943     return std::make_pair(true, Res);
    944   }
    945 
    946   }
    947 
    948   return std::make_pair(false, nullptr);
    949 }
    950 
    951 bool MipsSEDAGToDAGISel::
    952 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
    953                              std::vector<SDValue> &OutOps) {
    954   SDValue Base, Offset;
    955 
    956   switch(ConstraintID) {
    957   default:
    958     llvm_unreachable("Unexpected asm memory constraint");
    959   // All memory constraints can at least accept raw pointers.
    960   case InlineAsm::Constraint_i:
    961     OutOps.push_back(Op);
    962     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
    963     return false;
    964   case InlineAsm::Constraint_m:
    965     if (selectAddrRegImm16(Op, Base, Offset)) {
    966       OutOps.push_back(Base);
    967       OutOps.push_back(Offset);
    968       return false;
    969     }
    970     OutOps.push_back(Op);
    971     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
    972     return false;
    973   case InlineAsm::Constraint_R:
    974     // The 'R' constraint is supposed to be much more complicated than this.
    975     // However, it's becoming less useful due to architectural changes and
    976     // ought to be replaced by other constraints such as 'ZC'.
    977     // For now, support 9-bit signed offsets which is supportable by all
    978     // subtargets for all instructions.
    979     if (selectAddrRegImm9(Op, Base, Offset)) {
    980       OutOps.push_back(Base);
    981       OutOps.push_back(Offset);
    982       return false;
    983     }
    984     OutOps.push_back(Op);
    985     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
    986     return false;
    987   case InlineAsm::Constraint_ZC:
    988     // ZC matches whatever the pref, ll, and sc instructions can handle for the
    989     // given subtarget.
    990     if (Subtarget->inMicroMipsMode()) {
    991       // On microMIPS, they can handle 12-bit offsets.
    992       if (selectAddrRegImm12(Op, Base, Offset)) {
    993         OutOps.push_back(Base);
    994         OutOps.push_back(Offset);
    995         return false;
    996       }
    997     } else if (Subtarget->hasMips32r6()) {
    998       // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
    999       if (selectAddrRegImm9(Op, Base, Offset)) {
   1000         OutOps.push_back(Base);
   1001         OutOps.push_back(Offset);
   1002         return false;
   1003       }
   1004     } else if (selectAddrRegImm16(Op, Base, Offset)) {
   1005       // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
   1006       OutOps.push_back(Base);
   1007       OutOps.push_back(Offset);
   1008       return false;
   1009     }
   1010     // In all cases, 0-bit offsets are acceptable.
   1011     OutOps.push_back(Op);
   1012     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
   1013     return false;
   1014   }
   1015   return true;
   1016 }
   1017 
   1018 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
   1019   return new MipsSEDAGToDAGISel(TM);
   1020 }
   1021