| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 122 MachineInstrBuilder MIB;
124 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
129 MIB.addMemOperand(MMO);
130 MIB = BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg);
131 MIB.addReg(Reg, RegState::Kill).addImm(0);
132 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
133 AddDefaultPred(MIB);
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| Thumb2InstrInfo.cpp | 154 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
155 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
156 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
157 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
158 AddDefaultPred(MIB);
193 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
194 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
195 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
196 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
197 AddDefaultPred(MIB);
[all...] |
| ThumbRegisterInfo.cpp | 165 MachineInstrBuilder MIB =
168 MIB = AddDefaultT1CC(MIB);
170 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
172 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
173 AddDefaultPred(MIB);
306 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
308 MIB = AddDefaultT1CC(MIB);
309 MIB.addReg(BaseReg, RegState::Kill)
[all...] |
| MLxExpansionPass.cpp | 293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
297 MIB.addImm(LaneImm);
298 MIB.addImm(Pred).addReg(PredReg);
300 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
305 MIB.addReg(TmpReg, getKillRegState(true))
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
310 MIB.addImm(Pred).addReg(PredReg);
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| Thumb1FrameLowering.cpp | 454 MachineInstrBuilder MIB =
460 MIB.addOperand(MO);
461 MIB.addReg(ARM::PC, RegState::Define);
536 MachineInstrBuilder MIB =
543 MIB.addOperand(MO);
549 MBB.erase(MIB.getInstr());
584 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
585 AddDefaultPred(MIB);
603 MIB.addReg(Reg, getKillRegState(isKill));
605 MIB.setMIFlags(MachineInstr::FrameSetup)
[all...] |
| Thumb2ITBlockPass.cpp | 196 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
204 MachineBasicBlock::iterator InsertPos = MIB.getInstr();
253 MIB.addImm(Mask);
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPeephole.cpp | 112 MachineInstrBuilder MIB =
118 MBB.insert((MachineBasicBlock::iterator)&Root, MIB);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFixupHwLoops.cpp | 166 MachineInstrBuilder MIB;
184 MIB = BuildMI(*MBB, MII, DL, TII->get(newOp));
187 MIB.addOperand(MII->getOperand(i));
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| HexagonGenPredicate.cpp | 405 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
411 MIB.addReg(Pred.R, 0, Pred.S);
413 DEBUG(dbgs() << "generated: " << *MIB);
|
| /external/llvm/lib/CodeGen/ |
| ImplicitNullChecks.cpp | 366 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_LOAD_OP), DefReg)
371 MIB.addOperand(MO);
373 MIB.setMemRefs(LoadMI->memoperands_begin(), LoadMI->memoperands_end());
375 return MIB;
|
| MachineInstrBundle.cpp | 122 MachineInstrBuilder MIB =
124 Bundle.prepend(MIB);
203 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
212 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
|
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 284 MachineInstrBuilder MIB =
288 DEBUG(dbgs() << " adding copy: " << *MIB);
290 return MIB;
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| AArch64BranchRelaxation.cpp | 440 MachineInstrBuilder MIB = BuildMI(
445 MIB.addOperand(MI->getOperand(1));
447 invertBccCondition(MIB);
448 MIB.addMBB(NextBB);
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| AArch64ConditionalCompares.cpp | 656 MachineInstrBuilder MIB =
660 MIB.addImm(0); // cbz/cbnz Rn -> ccmp Rn, #0
662 MIB.addOperand(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate
663 MIB.addImm(NZCV).addImm(HeadCmpBBCC);
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| AArch64FrameLowering.cpp | [all...] |
| AArch64LoadStoreOptimizer.cpp | 718 MachineInstrBuilder MIB;
725 MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
731 concatenateMemOperands(MIB, I, Paired);
736 MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
744 (void)MIB;
760 MachineOperand &DstMO = MIB->getOperand(SExtIdx);
768 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
792 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
843 static bool mayAlias(MachineInstr *MIa, MachineInstr *MIb,
846 if (!MIa->mayStore() && !MIb->mayStore()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 102 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
106 MIB.addReg(Cond[i].getReg());
108 MIB.addImm(Cond[i].getImm());
112 MIB.addMBB(TBB);
280 MachineInstrBuilder MIB;
281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
284 MIB.addOperand(I->getOperand(J));
286 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
287 return MIB;
|
| Mips16InstrInfo.cpp | 84 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
87 MIB.addReg(DestReg, RegState::Define);
90 MIB.addReg(SrcReg, getKillRegState(KillSrc));
171 static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
185 MIB.addReg(Reg, Flags);
204 MachineInstrBuilder MIB;
206 MIB = BuildMI(MBB, I, DL, get(Opc));
208 addSaveRestoreRegs(MIB, CSI);
210 MIB.addReg(Mips::S2);
212 MIB.addImm(FrameSize)
[all...] |
| MipsLongBranch.cpp | 222 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
232 MIB.addReg(MO.getReg());
235 MIB.addMBB(MBBOpnd);
242 MIBundleBuilder(&*MIB).append((++II)->removeFromBundle());
|
| MipsSEInstrInfo.cpp | 167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
170 MIB.addReg(DestReg, RegState::Define);
173 MIB.addReg(SrcReg, getKillRegState(KillSrc));
176 MIB.addReg(ZeroReg);
|
| /external/llvm/lib/Target/X86/ |
| X86ExpandPseudo.cpp | 99 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
101 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
105 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
112 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
114 MIB.addOperand(MBBI->getOperand(i));
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 357 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
359 MIB.addReg(SP::G0);
360 MIB.addReg(Src);
361 MovMI = MIB.getInstr();
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 108 // Add GPR64 to the save instruction being built by MIB, which is in basic
112 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
119 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
178 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
181 addSavedGPR(MBB, MIB, LowGPR, false);
182 addSavedGPR(MBB, MIB, HighGPR, false);
185 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
192 addSavedGPR(MBB, MIB, Reg, true);
198 addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
248 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG))
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 263 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
264 MIB.addImm(Adjusted);
265 MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(),
400 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
403 MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
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