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      1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the Mips implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "MipsInstrInfo.h"
     15 #include "InstPrinter/MipsInstPrinter.h"
     16 #include "MipsAnalyzeImmediate.h"
     17 #include "MipsMachineFunction.h"
     18 #include "MipsSubtarget.h"
     19 #include "llvm/ADT/STLExtras.h"
     20 #include "llvm/CodeGen/MachineInstrBuilder.h"
     21 #include "llvm/CodeGen/MachineRegisterInfo.h"
     22 #include "llvm/Support/ErrorHandling.h"
     23 #include "llvm/Support/TargetRegistry.h"
     24 
     25 using namespace llvm;
     26 
     27 #define GET_INSTRINFO_CTOR_DTOR
     28 #include "MipsGenInstrInfo.inc"
     29 
     30 // Pin the vtable to this file.
     31 void MipsInstrInfo::anchor() {}
     32 
     33 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
     34     : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
     35       Subtarget(STI), UncondBrOpc(UncondBr) {}
     36 
     37 const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
     38   if (STI.inMips16Mode())
     39     return llvm::createMips16InstrInfo(STI);
     40 
     41   return llvm::createMipsSEInstrInfo(STI);
     42 }
     43 
     44 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
     45   return op.isImm() && op.getImm() == 0;
     46 }
     47 
     48 /// insertNoop - If data hazard condition is found insert the target nop
     49 /// instruction.
     50 void MipsInstrInfo::
     51 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
     52 {
     53   DebugLoc DL;
     54   BuildMI(MBB, MI, DL, get(Mips::NOP));
     55 }
     56 
     57 MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
     58                                                 unsigned Flag) const {
     59   MachineFunction &MF = *MBB.getParent();
     60   MachineFrameInfo &MFI = *MF.getFrameInfo();
     61   unsigned Align = MFI.getObjectAlignment(FI);
     62 
     63   return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
     64                                  Flag, MFI.getObjectSize(FI), Align);
     65 }
     66 
     67 //===----------------------------------------------------------------------===//
     68 // Branch Analysis
     69 //===----------------------------------------------------------------------===//
     70 
     71 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
     72                                   MachineBasicBlock *&BB,
     73                                   SmallVectorImpl<MachineOperand> &Cond) const {
     74   assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
     75   int NumOp = Inst->getNumExplicitOperands();
     76 
     77   // for both int and fp branches, the last explicit operand is the
     78   // MBB.
     79   BB = Inst->getOperand(NumOp-1).getMBB();
     80   Cond.push_back(MachineOperand::CreateImm(Opc));
     81 
     82   for (int i=0; i<NumOp-1; i++)
     83     Cond.push_back(Inst->getOperand(i));
     84 }
     85 
     86 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
     87                                   MachineBasicBlock *&TBB,
     88                                   MachineBasicBlock *&FBB,
     89                                   SmallVectorImpl<MachineOperand> &Cond,
     90                                   bool AllowModify) const {
     91   SmallVector<MachineInstr*, 2> BranchInstrs;
     92   BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
     93 
     94   return (BT == BT_None) || (BT == BT_Indirect);
     95 }
     96 
     97 void
     98 MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
     99                            DebugLoc DL, ArrayRef<MachineOperand> Cond) const {
    100   unsigned Opc = Cond[0].getImm();
    101   const MCInstrDesc &MCID = get(Opc);
    102   MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
    103 
    104   for (unsigned i = 1; i < Cond.size(); ++i) {
    105     if (Cond[i].isReg())
    106       MIB.addReg(Cond[i].getReg());
    107     else if (Cond[i].isImm())
    108       MIB.addImm(Cond[i].getImm());
    109     else
    110        assert(true && "Cannot copy operand");
    111   }
    112   MIB.addMBB(TBB);
    113 }
    114 
    115 unsigned MipsInstrInfo::InsertBranch(
    116     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
    117     ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
    118   // Shouldn't be a fall through.
    119   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
    120 
    121   // # of condition operands:
    122   //  Unconditional branches: 0
    123   //  Floating point branches: 1 (opc)
    124   //  Int BranchZero: 2 (opc, reg)
    125   //  Int Branch: 3 (opc, reg0, reg1)
    126   assert((Cond.size() <= 3) &&
    127          "# of Mips branch conditions must be <= 3!");
    128 
    129   // Two-way Conditional branch.
    130   if (FBB) {
    131     BuildCondBr(MBB, TBB, DL, Cond);
    132     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
    133     return 2;
    134   }
    135 
    136   // One way branch.
    137   // Unconditional branch.
    138   if (Cond.empty())
    139     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
    140   else // Conditional branch.
    141     BuildCondBr(MBB, TBB, DL, Cond);
    142   return 1;
    143 }
    144 
    145 unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
    146   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
    147   MachineBasicBlock::reverse_iterator FirstBr;
    148   unsigned removed;
    149 
    150   // Skip all the debug instructions.
    151   while (I != REnd && I->isDebugValue())
    152     ++I;
    153 
    154   FirstBr = I;
    155 
    156   // Up to 2 branches are removed.
    157   // Note that indirect branches are not removed.
    158   for (removed = 0; I != REnd && removed < 2; ++I, ++removed)
    159     if (!getAnalyzableBrOpc(I->getOpcode()))
    160       break;
    161 
    162   MBB.erase(I.base(), FirstBr.base());
    163 
    164   return removed;
    165 }
    166 
    167 /// ReverseBranchCondition - Return the inverse opcode of the
    168 /// specified Branch instruction.
    169 bool MipsInstrInfo::ReverseBranchCondition(
    170     SmallVectorImpl<MachineOperand> &Cond) const {
    171   assert( (Cond.size() && Cond.size() <= 3) &&
    172           "Invalid Mips branch condition!");
    173   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
    174   return false;
    175 }
    176 
    177 MipsInstrInfo::BranchType MipsInstrInfo::AnalyzeBranch(
    178     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
    179     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
    180     SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
    181 
    182   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
    183 
    184   // Skip all the debug instructions.
    185   while (I != REnd && I->isDebugValue())
    186     ++I;
    187 
    188   if (I == REnd || !isUnpredicatedTerminator(&*I)) {
    189     // This block ends with no branches (it just falls through to its succ).
    190     // Leave TBB/FBB null.
    191     TBB = FBB = nullptr;
    192     return BT_NoBranch;
    193   }
    194 
    195   MachineInstr *LastInst = &*I;
    196   unsigned LastOpc = LastInst->getOpcode();
    197   BranchInstrs.push_back(LastInst);
    198 
    199   // Not an analyzable branch (e.g., indirect jump).
    200   if (!getAnalyzableBrOpc(LastOpc))
    201     return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
    202 
    203   // Get the second to last instruction in the block.
    204   unsigned SecondLastOpc = 0;
    205   MachineInstr *SecondLastInst = nullptr;
    206 
    207   if (++I != REnd) {
    208     SecondLastInst = &*I;
    209     SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
    210 
    211     // Not an analyzable branch (must be an indirect jump).
    212     if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
    213       return BT_None;
    214   }
    215 
    216   // If there is only one terminator instruction, process it.
    217   if (!SecondLastOpc) {
    218     // Unconditional branch.
    219     if (LastOpc == UncondBrOpc) {
    220       TBB = LastInst->getOperand(0).getMBB();
    221       return BT_Uncond;
    222     }
    223 
    224     // Conditional branch
    225     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
    226     return BT_Cond;
    227   }
    228 
    229   // If we reached here, there are two branches.
    230   // If there are three terminators, we don't know what sort of block this is.
    231   if (++I != REnd && isUnpredicatedTerminator(&*I))
    232     return BT_None;
    233 
    234   BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
    235 
    236   // If second to last instruction is an unconditional branch,
    237   // analyze it and remove the last instruction.
    238   if (SecondLastOpc == UncondBrOpc) {
    239     // Return if the last instruction cannot be removed.
    240     if (!AllowModify)
    241       return BT_None;
    242 
    243     TBB = SecondLastInst->getOperand(0).getMBB();
    244     LastInst->eraseFromParent();
    245     BranchInstrs.pop_back();
    246     return BT_Uncond;
    247   }
    248 
    249   // Conditional branch followed by an unconditional branch.
    250   // The last one must be unconditional.
    251   if (LastOpc != UncondBrOpc)
    252     return BT_None;
    253 
    254   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
    255   FBB = LastInst->getOperand(0).getMBB();
    256 
    257   return BT_CondUncond;
    258 }
    259 
    260 /// Return the number of bytes of code the specified instruction may be.
    261 unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
    262   switch (MI->getOpcode()) {
    263   default:
    264     return MI->getDesc().getSize();
    265   case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
    266     const MachineFunction *MF = MI->getParent()->getParent();
    267     const char *AsmStr = MI->getOperand(0).getSymbolName();
    268     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
    269   }
    270   case Mips::CONSTPOOL_ENTRY:
    271     // If this machine instr is a constant pool entry, its size is recorded as
    272     // operand #2.
    273     return MI->getOperand(2).getImm();
    274   }
    275 }
    276 
    277 MachineInstrBuilder
    278 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
    279                                   MachineBasicBlock::iterator I) const {
    280   MachineInstrBuilder MIB;
    281   MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
    282 
    283   for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J)
    284     MIB.addOperand(I->getOperand(J));
    285 
    286   MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
    287   return MIB;
    288 }
    289